Kip Macsai-Goren
e209dbcf50
some cleanup of signals, not done yet
2021-06-08 13:39:32 -04:00
Kip Macsai-Goren
3493027bf5
added shared constants file list of includes
2021-06-04 17:05:47 -04:00
Kip Macsai-Goren
1ae529c450
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
David Harris
a26bf37be8
Started MMU
2021-06-04 11:59:14 -04:00
David Harris
4f71964529
Fixed RV32 MMU constants
2021-06-04 09:15:42 -04:00
David Harris
0674f5506e
moved shared constants to a shared directory
2021-06-03 22:41:30 -04:00
Kip Macsai-Goren
8fb2ee6e86
added support for sv48 and some docs on how to use these files
2021-06-03 14:32:12 -04:00
Kip Macsai-Goren
1ea9b94cf1
added tests for SV48 and translation off with vmem
2021-06-03 14:28:52 -04:00
bbracker
ad3b103a86
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-03 10:03:26 -04:00
bbracker
4e765ee1c5
expanded GPIO testing and caught small GPIO bug
2021-06-03 10:03:09 -04:00
bbracker
a7e15f4c23
reached a good stopping point on buildroot progress; parse_qemu.py has been rewritten for readability and QEMU MMU failure workaround
2021-06-03 10:00:16 -04:00
Ross Thompson
e50a1ef5e4
Fixed a few lint errors,
...
clock gater was wrong,
missing signal definitions in branch predictor.
2021-06-02 09:33:24 -05:00
bbracker
a683dd7fde
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-02 10:03:23 -04:00
bbracker
2c77a13c08
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
Kip Macsai-Goren
5187574e8a
implemented Sv48.
2021-06-01 17:50:37 -04:00
Kip Macsai-Goren
40cfa86935
Edited and added constants to support SV48
2021-06-01 17:49:45 -04:00
James E. Stine
eba7ce64f5
delete div.bak
2021-06-01 17:39:54 -04:00
Ross Thompson
babcea195a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 15:20:37 -05:00
Ross Thompson
0670c57fd2
The clock gater was not implemented correctly. Now it is level sensitive to a low clock.
2021-06-01 15:05:22 -05:00
James E. Stine
564d7c4adb
Minor cosmetic update to fpu.sv
2021-06-01 15:45:32 -04:00
James E. Stine
2eeb12c674
Updates to muldiv.sv for 32-bit div/rem
2021-06-01 15:31:07 -04:00
Ross Thompson
fe22fd2db8
added clock gater to floating point divider to speed up simulation time.
2021-06-01 13:46:21 -05:00
Ross Thompson
7f1653f073
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 12:42:21 -05:00
Ross Thompson
997c13a521
Forgot to include the new gshare predictor file.
2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
fac2431add
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-01 13:20:39 -04:00
Ross Thompson
ab509614bb
Changed to bp config to use gshare.
2021-06-01 12:14:58 -05:00
Ross Thompson
89ad4477e4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 11:33:12 -05:00
Ross Thompson
857f59ab5c
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
James E. Stine
ddbdd0d5a2
Modify muldiv.sv to handle W instructions for 64-bits
2021-05-31 23:27:42 -04:00
Ross Thompson
f6c88666cf
may have fixed the global branch history predictor.
...
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
0fe63282f8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-31 11:01:15 -04:00
James E. Stine
46a232b862
Cosmetic changes on integer divider
2021-05-31 09:16:30 -04:00
James E. Stine
9954d16fc9
Add enhancements to integer divider including:
...
- better comments
- optimize FSM to end earlier
- passes for 32-bit or 64-bit depending on parameter to intdiv
Left div.bak in just in case have to revert back to original for now.
2021-05-31 09:12:21 -04:00
James E. Stine
12c34c25f3
Modify elements of generics for LZD and shifter wrote for integer
...
divider.
2021-05-31 08:36:19 -04:00
bbracker
39ae743543
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Kip Macsai-Goren
690815ca51
made priority encoder parameterizable
2021-05-28 18:09:28 -04:00
Ross Thompson
8a035104ac
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
Katherine Parry
778ba6bbf5
classify unit created and passes imperas tests
2021-05-27 18:53:55 -04:00
Katherine Parry
1459d840ed
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Ross Thompson
7e84c3f514
Updated benchmarking code.
2021-05-27 11:48:29 -05:00
Katherine Parry
309e6c3dc1
FADD and FSUB imperas tests pass
2021-05-26 12:33:33 -04:00
James E. Stine
bb99480fca
delete old file for FPregfile
2021-05-26 09:13:09 -05:00
James E. Stine
77260643eb
Add regression test for fpadd
2021-05-26 09:12:37 -05:00
Katherine Parry
e7190b0690
renamed top level FPU wires
2021-05-25 20:04:34 -04:00
Kip Macsai-Goren
33cd133a65
completed mstatus test for rv32p, rv64p, updated testbench to reflect
2021-05-25 15:44:52 -04:00
Kip Macsai-Goren
45e7628e90
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-25 15:28:19 -04:00
Ross Thompson
fec40a1b75
fixed bug with icache miss spill fsm branch.
2021-05-25 14:26:22 -05:00
James E. Stine
bb5404e14a
Update FPregfile to use more compact code and better structure for ease in reading
2021-05-25 13:21:59 -05:00
Ross Thompson
063e458ff0
Merge remote-tracking branch 'refs/remotes/origin/main' into main
2021-05-24 23:25:36 -05:00
Ross Thompson
16e037b8e9
Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.
2021-05-24 23:24:54 -05:00
