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Configurable RISC-V Processor
886 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
f6c88666cf
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Ross Thompson f6c88666cf may have fixed the global branch history predictor. 
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
2021-05-31 16:11:12 -05:00
riscv-coremark commit ehedenberg coremark 2021-05-17 18:02:35 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP may have fixed the global branch history predictor. 2021-05-31 16:11:12 -05:00
wally-pipelined may have fixed the global branch history predictor. 2021-05-31 16:11:12 -05:00
.gitignore script for running make and logging output 2021-05-17 22:12:18 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor