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Fixed bug on icache spill. if the cpu stalled on the completion it was possible to use the wrong address for the sram read. Also miss spill hit always selected the wrong address.

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This commit is contained in:
Ross Thompson 2021-12-20 23:27:37 -06:00
parent 6acf6257e4
commit ffe792bcfc
1 changed files with 2 additions and 2 deletions
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4
wally-pipelined/src/cache/icachefsm.sv vendored
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@ -294,8 +294,8 @@ module icachefsm
ICacheStallF = 1'b0;
LRUWriteEn = 1'b1;
if(StallF) begin
NextState = STATE_CPU_BUSY;
SelAdr = 2'b01;
NextState = STATE_CPU_BUSY_SPILL;
SelAdr = 2'b10;
end else begin
NextState = STATE_READY;
end