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Author SHA1 Message Date
Ross Thompson
e5d624c1fa Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
fd1de6b047 Updated wave file. 2021-07-15 11:04:49 -05:00
Ross Thompson
b9902b0560 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
8610ef204c Renamed DCacheStall to LSUStall in hart and hazard. 
Added missing logic in lsu.
 2021-07-15 10:16:16 -05:00
Kip Macsai-Goren
74e67df080 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-15 10:52:39 -04:00
Ross Thompson
704f4f724e dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
ba1e1ec231 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
c74d26eea4 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
c79650b508 Added d cache StallW checks for any time the cache wants to go to STATE_READY. 2021-07-14 17:25:50 -05:00
Ross Thompson
2c946a282f Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Katherine Parry
f5bfdf46db fpu unpacking unit created 2021-07-14 17:56:49 -04:00
Kip Macsai-Goren
dd313d57c0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-14 17:30:45 -04:00
Ross Thompson
e91501985c Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
adce800041 Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled. 2021-07-14 15:47:38 -05:00
Ross Thompson
d78e31e9df Forgot to include one hot decoder. 2021-07-14 15:46:52 -05:00
Ross Thompson
f4295ff097 Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. 
This solves the committedM issue.
 2021-07-14 15:00:33 -05:00
bbracker
335afb14e7 testvector unlinker for dev purposes 2021-07-14 11:05:34 -04:00
James Stine
e6d19be87c put back for now to test fdiv 2021-07-14 06:48:29 -05:00
Abe
782344cfd9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-14 04:47:31 -04:00
Abe
ac92823c8d Commented out remaining ehitoa function declaration/calls and related char buff instances. Also commented out extra libraries not currently in use 2021-07-14 04:46:11 -04:00
bbracker
46e704b7ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-14 00:21:39 -04:00
bbracker
92899b33f8 make testvector scripts agree with new file structure; use symbols to determine end of linux boot 2021-07-14 00:21:29 -04:00
Ross Thompson
9b756d6a94 Implemented uncached reads. 2021-07-13 23:03:09 -05:00
Ross Thompson
e8bf502bc2 Added CommitedM to data cache output. 2021-07-13 22:43:42 -05:00
bbracker
28887bb3d5 needed to create a directory for gdb script 2021-07-13 19:39:57 -04:00
Ross Thompson
3e57c899a2 Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
Abe
9f9b38db9f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 18:22:36 -04:00
Kip Macsai-Goren
9d83566637 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 17:41:47 -04:00
James E. Stine
46001fef27 mod 2 of fpdivsqrt update 2021-07-13 16:59:17 -04:00
James E. Stine
8382a17969 Update fpdivsqrt item until move into uarch 2021-07-13 16:53:20 -04:00
bbracker
f2bf4920d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 16:16:04 -04:00
bbracker
64d22753b5 changed QEMU to use different ports 2021-07-13 16:15:51 -04:00
Ross Thompson
baa2b5d15f Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. 2021-07-13 14:51:42 -05:00
Ross Thompson
3c1a717399 Fixed the fetch buffer accidental overwrite on eviction. 2021-07-13 14:21:29 -05:00
Ross Thompson
32f27cfecf Dcache AHB address generation was wrong. Needed to zero the offset. 2021-07-13 14:19:04 -05:00
Ross Thompson
afc1bc9c38 Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
David Harris
9de97c1e20 Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
Ross Thompson
47e16f5629 Fixed back to back store issue. 
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
 2021-07-13 12:46:20 -05:00
Abe
46e1a008c3 Downloaded clean version of Coremark from EEMBC github page with which to benchmark RISCV-Wally 2021-07-13 13:37:40 -04:00
David Harris
2ba82d1a5c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:26:51 -04:00
David Harris
223086ac33 added or.sv 2021-07-13 13:26:40 -04:00
Katherine Parry
ca19b2e215 Fixed writting MStatus FS bits 2021-07-13 13:22:04 -04:00
Katherine Parry
efdec72df1 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
David Harris
93d6688c3c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:19:24 -04:00
David Harris
b5dddec858 Fixed InstrValid from W to M stage for CSR performance counters 2021-07-13 13:19:13 -04:00
bbracker
3565580f40 updated buildroot make procedure to incorporate configs more robustly 2021-07-13 12:40:14 -04:00
Ross Thompson
224e3b2991 Fixed subword write. subword read should not feed into subword write. 2021-07-13 11:21:44 -05:00
Ross Thompson
30b7c4436c restored rv64ic config back to full sized dtim. 2021-07-13 11:18:54 -05:00
Ross Thompson
3951eb56f5 Modularized the shadow memory to reduce performance hit. 2021-07-13 10:55:57 -05:00