Ross Thompson
57a7074800
Some progress. Had to change how the page table walker got it's ready.
2021-06-25 15:07:41 -05:00
Kip Macsai-Goren
d7e518991e
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
Ross Thompson
aeeaf6d919
Progress.
2021-06-24 13:05:22 -05:00
Kip Macsai-Goren
c8f80967a6
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Ross Thompson
f74ecbb81e
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
David Harris
fa51ab9f68
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6be0a3b8df
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
bbracker
fc851ca795
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-22 18:28:30 -04:00
bbracker
303f8e2a7f
give EBU a dedicated PMA unit as just an address decoder
2021-06-22 18:28:08 -04:00
Katherine Parry
353a27f12f
rv64f FLW passes imperas tests
2021-06-22 16:36:16 -04:00
David Harris
1ec90a5e1f
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
David Harris
580ac1c4df
Made MemPAdrM and related signals PA_BITS wide
2021-06-18 09:36:22 -04:00
David Harris
336936cc39
Cleaned up name of MTIME register in CSRC
2021-06-18 07:53:49 -04:00
bbracker
5a661a7392
provide time and timeh CSRs based on CLINT's counter
2021-06-17 08:38:30 -04:00
David Harris
90e5781471
Start to parameterize number of PMP Entries
2021-06-08 15:29:22 -04:00
bbracker
cc91c774a6
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
2021-06-08 12:41:25 -04:00
bbracker
e7e4105931
* GPIO comprehensive testing
...
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
2021-06-08 12:32:46 -04:00
David Harris
ff62000e2c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
Katherine Parry
75a6097467
fixed lint warnings for fpu and lzd
2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
49200bd922
Cleaned up some unused signals
2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
1ae529c450
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
bbracker
2c77a13c08
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
bbracker
39ae743543
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Katherine Parry
1459d840ed
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Katherine Parry
e7190b0690
renamed top level FPU wires
2021-05-25 20:04:34 -04:00
Katherine Parry
90d5fdba04
FMV.X.D imperas test passes
2021-05-24 14:44:30 -04:00
Katherine Parry
70968a4ec3
FSD and FLD imperas tests pass
2021-05-23 18:33:14 -04:00
Katherine Parry
06af239e6c
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
Katherine Parry
9464c9022d
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
Thomas Fleming
ea4e76938e
Remove busy-mmu and fix missing signal
2021-05-14 07:14:20 -04:00
Thomas Fleming
cfe64e7c24
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Katherine Parry
db95151d8d
fpu imperas tests run
2021-05-01 02:18:01 +00:00
Thomas Fleming
5f2bccd88f
Clean up PMA checker and begin PMP checker
2021-04-29 02:20:39 -04:00
Ross Thompson
6e803b724e
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Ross Thompson
27ef10df07
almost working icache.
2021-04-23 16:47:23 -05:00
Ross Thompson
020fb65adf
Fixed icache for 32 bit.
...
Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Thomas Fleming
38236e9172
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Thomas Fleming
ef80176e2c
Extend stall on leaf page lookups
2021-04-22 01:51:38 -04:00
Thomas Fleming
4bae666fa1
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Jarred Allen
c1e2e58ebe
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
2021-04-14 18:24:32 -04:00
Thomas Fleming
09c9c49541
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/pagetablewalker.sv
2021-04-13 13:42:03 -04:00
Thomas Fleming
6188f10732
Move InstrPageFault to fetch stage
2021-04-13 13:39:22 -04:00
Teo Ene
1018a10625
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Jarred Allen
d99b8f772e
Merge from branch 'main'
2021-04-08 17:19:34 -04:00
Thomas Fleming
303c2c4839
Implement support for superpages
2021-04-08 02:44:59 -04:00
Ross Thompson
c91436d3b7
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Thomas Fleming
6b43381c38
Comment out fpu from hart until module exists
2021-04-03 22:34:11 -04:00
Thomas Fleming
dbd5a4320e
Merge branch 'mmu' into main
...
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
2021-04-03 22:12:52 -04:00
Thomas Fleming
1cbdaf1f05
Fix extraneous page fault stall
2021-04-03 21:28:24 -04:00
