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947 Commits

Author SHA1 Message Date
bbracker
1824b2af13 fix div restarting bug 2021-10-07 18:55:00 -04:00
James E. Stine
a91c0c8fc7 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
David Harris
36bbf0c502 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
10ef563211 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
78eba19a1f Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
48e33c79a9 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
648cc8ef64 Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
2ae51d1852 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
81601e26a3 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
c690a863b5 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
David Harris
0c08a7c05c More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
5e6b2490cb Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
418e9cd6e6 Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
b3bded9e6c Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
5db800fac3 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
3a85c972b6 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
5d64f04752 Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
f913305993 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
afd6babc13 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
e33ef58e67 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
4926ae343a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
852eb24731 Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
9d63aa683f Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
fbe6e41169 Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
e11c565a6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
6aa79657ed Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit fec96218f6.
 2021-09-30 20:45:26 -04:00
David Harris
caa36f267d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
9d8e7f2714 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
760f4d66dd RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
David Harris
42d573be57 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
fec96218f6 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
Ross Thompson
221dbe92b2 Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
Ross Thompson
e16c27225b Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00
Ross Thompson
cfd522da6b The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
Ross Thompson
0b1e59d075 Updated Dcache to fully support flush. This appears to work. 
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
 2021-09-17 10:25:21 -05:00
Ross Thompson
615fd41e7b Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
348187ea70 Added counters to walk through d cache flush. 2021-09-16 17:12:51 -05:00
Ross Thompson
d901f60a6d Added flush controls to cachway. 2021-09-16 16:56:48 -05:00
Ross Thompson
cae350abb7 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
David Harris
9ae25b0cea Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
David Harris
9fa048980d Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
David Harris
bbb6c7bef7 Restored old integer divider 2021-09-12 22:07:52 -04:00
David Harris
dd1e7548ed Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
Ross Thompson
be864abcc5 Fixed bug with or_rows. 
If ROWS == 1 then the output was always X.  Fixed by adding if to check if ROWS==1.
 2021-09-11 15:51:11 -05:00
Ross Thompson
570aab4275 Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches. 2021-09-11 15:40:27 -05:00
Ross Thompson
5744796431 Fixed dcache to prevent latches in FPGA synthesized design. 2021-09-11 12:03:48 -05:00
Ross Thompson
6f4542f063 Third attempt at fixing the write enables for the icache cacheway. 2021-09-09 15:08:10 -05:00
Ross Thompson
6965bde95c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Refixed some bit width issues in the icache.
 2021-09-09 12:44:02 -05:00
Ross Thompson
1d370ca71f fixed some lint bugs. 2021-09-09 12:38:57 -05:00
David Harris
12bd351edf Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00