David Harris
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690410721d
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Cleaning up CoreMark benchmark
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2021-11-18 20:12:52 -08:00 |
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David Harris
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8e8b84f532
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vert "Simplifying riscv-coremark"
This reverts commit ce8232e396.
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2021-11-18 18:40:13 -08:00 |
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David Harris
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ce8232e396
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Simplifying riscv-coremark
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2021-11-18 17:15:40 -08:00 |
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David Harris
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b73e6354e3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-18 16:14:42 -08:00 |
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David Harris
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402b473dbb
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CoreMark testing
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2021-11-18 16:14:25 -08:00 |
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slmnemo
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0bf1836a3a
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Removed .* from hazard hzu(.*).
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2021-11-17 14:21:23 -08:00 |
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slmnemo
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5c28553ca1
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Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
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2021-11-17 14:08:08 -08:00 |
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slmnemo
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df6c54a664
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 13:38:51 -08:00 |
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slmnemo
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bf8cef78bc
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removed .* from muldiv.sv (REAL)
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2021-11-17 13:37:50 -08:00 |
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David Harris
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0a281a06e0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 13:28:33 -08:00 |
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Noah Limpert
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b63c0f35d1
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ieu variable naming changed for clarity
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2021-11-17 13:24:28 -08:00 |
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slmnemo
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c5c886ddc1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 13:23:20 -08:00 |
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slmnemo
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40efffc70b
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Removed .*s from muldiv.sv
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2021-11-17 13:23:12 -08:00 |
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Noah Limpert
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bbd17e730b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 13:04:33 -08:00 |
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Noah Limpert
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70a84b56c8
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Updated IFU variable naming for clarity
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2021-11-17 12:39:05 -08:00 |
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Kevin Kim
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6437c04074
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 12:18:25 -08:00 |
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Kevin Kim
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38437c664e
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root level makefile added
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2021-11-17 12:17:56 -08:00 |
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Kip Macsai-Goren
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7a8c21e71f
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renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
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2021-11-17 10:53:17 -08:00 |
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Skylar Litz
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6fde97b16c
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fixed interrupt timing bug
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2021-11-16 16:46:17 -08:00 |
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David Harris
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c610be25a7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-16 12:30:55 -08:00 |
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bbracker
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2203590f9f
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get current privilege level from GDB for checkpoints
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2021-11-15 14:49:00 -08:00 |
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Skylar Litz
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3dd83b3113
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fix timing of delayed interrupt
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2021-11-11 09:35:51 -08:00 |
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David Harris
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570f24a9e4
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bringing Coremark back to life
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2021-11-10 12:43:31 -08:00 |
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Kevin Kim
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7cb8b76ef6
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Makefile added in regression directory:
-cd's into imperas then runs make commands, finally running the tvLinker script
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2021-11-09 10:55:48 -08:00 |
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bbracker
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f6a555009b
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increase expectations for buildroot and timeout count
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2021-11-06 14:57:29 -07:00 |
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bbracker
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c92d41a597
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checkpoint MIDELEG support
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2021-11-06 03:44:23 -07:00 |
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bbracker
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bc6332a780
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fix merge conflict
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2021-11-05 23:42:15 -07:00 |
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bbracker
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17e776f853
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checkpoints now use binary ram files
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2021-11-05 22:37:05 -07:00 |
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Kevin
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11efaa2669
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changed code aligner to run recursively on a root directory
-only runs the aligner on .sv files
-runs recursively on sub-directories
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2021-11-03 10:49:34 -07:00 |
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bbracker
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0c7681b942
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fix testbench interrupt timing
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2021-11-02 21:19:12 -07:00 |
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bbracker
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526aff54a8
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linux testgen refactor
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2021-11-01 14:09:49 -07:00 |
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David Harris
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d7f0abca5a
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Add3d wally32i test
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2021-11-01 13:17:49 -07:00 |
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David Harris
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dda035891a
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PIPELINE test running
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2021-11-01 12:44:35 -07:00 |
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David Harris
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60573b92b2
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Adding custom Wally test infrastructure
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2021-11-01 08:48:46 -07:00 |
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bbracker
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fe2cda493c
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fix buildroot graphical sim
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2021-10-31 18:33:43 -07:00 |
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David Harris
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360930fe8b
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Fixed exe2memfile parsing of weird line in arch64d test
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2021-10-30 07:26:18 -07:00 |
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David Harris
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bd1a4769ab
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-29 22:32:08 -07:00 |
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David Harris
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247f247ad3
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tesgen cleanup, added riscv-arch-test D tests
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2021-10-29 22:31:48 -07:00 |
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David Harris
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14b9b8126e
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rearranging testgen
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2021-10-29 22:28:37 -07:00 |
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Ross Thompson
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9c875d38a9
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Fixed the 4 way set associative pseudo LRU replacement policy.
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2021-10-29 12:46:02 -05:00 |
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Ross Thompson
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41dbb59e24
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Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.
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2021-10-29 11:03:37 -05:00 |
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Ross Thompson
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35fcadbe7f
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Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.
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2021-10-28 11:07:18 -05:00 |
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bbracker
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7158bf1d4f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-27 14:40:31 -07:00 |
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bbracker
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ab711c498d
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checkpoint generator off-by-one error fix
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2021-10-27 14:10:29 -07:00 |
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Noah Limpert
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27251a9935
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Have replaced .* with signal names in ifu
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2021-10-27 13:45:37 -07:00 |
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koooo142857
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33f5de0f5c
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aligned all files in ifu folder
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2021-10-27 12:43:55 -07:00 |
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David Harris
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7df4b0c8e7
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commented out some failing FPU tests
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2021-10-27 11:27:34 -07:00 |
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David Harris
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582c2bf37b
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Fixed FResultSelM to select proper flags
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2021-10-27 11:02:42 -07:00 |
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David Harris
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589bee5875
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-27 10:37:46 -07:00 |
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David Harris
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5783e47e1a
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Changes for floating point sims
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2021-10-27 10:37:35 -07:00 |
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