17 Commits

Author	SHA1	Message	Date
bbracker	f272cd46d8	peripheral lint fixes	2021-06-10 10:19:10 -04:00
bbracker	d4aeb1c387	merge	2021-06-10 10:03:01 -04:00
bbracker	79e798a641	UART improved and added more reg read side effects	2021-06-10 09:53:48 -04:00
David Harris	01d6ca1e2a	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
bbracker	e7e4105931	* GPIO comprehensive testing ... * MEPC more aware if M stage has actually committed * UART interrupt testing progress * UART added read IIR side effect of lowering THRE intr	2021-06-08 12:32:46 -04:00
David Harris	afd6153044	Rolled back fflush on uart. Use -syncio in Modelsim command line instead.	2021-05-03 20:04:44 -04:00
David Harris	d07a7fd0f8	Flush uart print statements on \n	2021-05-03 19:51:51 -04:00
David Harris	93466a0b2a	Flush uart print statements on \n	2021-05-03 19:41:37 -04:00
David Harris	58ce0fbbcc	Flush uart print statements on \n	2021-05-03 19:37:45 -04:00
David Harris	233726e8d8	Flush uart print statements on \n	2021-05-03 19:25:28 -04:00
bbracker	a3487a9e47	do script refactor	2021-04-24 09:32:09 -04:00
bbracker	368c94d4ff	working GPIO interrupt demo	2021-04-15 21:09:15 -04:00
bbracker	0f4a231543	first merge of ahb fix	2021-03-05 14:24:22 -05:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
bbracker	9231646fb3	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00