David Harris
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8afc054e74
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 16:27:36 -08:00 |
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David Harris
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ed39099405
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reorder tests
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2022-12-01 16:27:33 -08:00 |
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Ross Thompson
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1d9b5badee
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Properly flush cacheLRU.
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2022-12-01 17:32:58 -06:00 |
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David Harris
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f64c0589fe
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FPU test list
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2022-12-01 10:18:36 -08:00 |
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Ross Thompson
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da92cdccd0
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 11:47:54 -06:00 |
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Ross Thompson
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cb310bfb1d
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Removed unused port on cacheway.
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2022-12-01 11:47:48 -06:00 |
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David Harris
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558f0b655e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 08:15:51 -08:00 |
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David Harris
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4e5f62a5c1
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code cleanup
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2022-12-01 08:15:48 -08:00 |
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Ross Thompson
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b0b16acaf5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 17:19:04 -06:00 |
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David Harris
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aa26a97b36
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signal sufixes in integer division
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2022-11-30 15:15:37 -08:00 |
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Ross Thompson
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f9ffcf377b
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Reverted the IROM/DTIM address range modelsim assignment.
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2022-11-30 17:13:33 -06:00 |
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Ross Thompson
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bfd238a4fc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 13:30:37 -06:00 |
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Ross Thompson
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813b2963fb
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More optimization.
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2022-11-30 11:26:48 -06:00 |
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Ross Thompson
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da7b13ba0a
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Removed reset on dirty cache bits.
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2022-11-30 11:04:37 -06:00 |
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Ross Thompson
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5e5cca6ae1
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Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
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2022-11-30 11:01:25 -06:00 |
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Ross Thompson
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ac3e02692b
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Preparing to merge dirty and tag srams.
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2022-11-30 10:40:48 -06:00 |
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Ross Thompson
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8692ccbafb
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Intermediate commit. Replaced flip flop dirty bit array with sram.
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2022-11-30 00:08:31 -06:00 |
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cturek
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e28a6901a9
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div tests in sim-wally
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2022-11-30 02:32:04 +00:00 |
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Ross Thompson
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e3577781b0
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Optimization of cacheway.
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2022-11-29 18:30:47 -06:00 |
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Ross Thompson
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1e2180ef98
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Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
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2022-11-29 17:19:31 -06:00 |
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Ross Thompson
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5e550fe5e6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 14:57:38 -06:00 |
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Ross Thompson
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9e4166407b
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Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
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2022-11-29 14:51:09 -06:00 |
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Ross Thompson
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179d321683
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Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
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2022-11-29 14:09:48 -06:00 |
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Kip Macsai-Goren
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66fcb2bffe
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 10:43:44 -08:00 |
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Kip Macsai-Goren
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26b4147f40
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added failing satp invalid tests to regression
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2022-11-29 10:43:38 -08:00 |
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Ross Thompson
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34bff09721
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 11:52:35 -06:00 |
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Ross Thompson
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ed54959378
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Renamed signals in the cache.
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2022-11-29 10:52:40 -06:00 |
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Kip Macsai-Goren
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af00eadec2
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added tests for invalid address being written to satp. Not passing regression
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2022-11-27 13:22:35 -08:00 |
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Ross Thompson
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4e52755c9f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-22 18:07:32 -06:00 |
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cturek
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7140642c93
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Almost done with Int division
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2022-11-22 22:22:59 +00:00 |
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cturek
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3fbccbf119
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Updated testbench/wave for fdivsqrt new start signals
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2022-11-22 22:22:26 +00:00 |
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Ross Thompson
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1736983557
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Cleanup cacheLRU.
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2022-11-22 14:59:01 -06:00 |
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Ross Thompson
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2ae7b555be
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File name change for cachereplacement policy to cacheLRU
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2022-11-20 22:35:02 -06:00 |
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Ross Thompson
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84679c0062
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Signal name changes for LRU.
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2022-11-20 22:31:36 -06:00 |
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Ross Thompson
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55335d1db6
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Updated top level fpga file.
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2022-11-18 11:10:45 -06:00 |
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Ross Thompson
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840517a582
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-17 17:45:59 -06:00 |
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Ross Thompson
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736a30afac
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Missing a file. Last commit will fail.
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2022-11-17 17:45:41 -06:00 |
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Ross Thompson
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4fbda554ee
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-17 17:38:52 -06:00 |
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Ross Thompson
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a1f39a8186
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Finally have the correct replacement policy implementation.
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2022-11-17 17:36:37 -06:00 |
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Ross Thompson
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8692bafd04
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Updated fpga wave configuration.
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2022-11-16 15:57:19 -06:00 |
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Ross Thompson
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b108e0a594
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-16 15:39:17 -06:00 |
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Ross Thompson
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ac0f6ddb7b
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I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
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2022-11-16 15:38:37 -06:00 |
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Ross Thompson
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9b2236b2a0
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Progress on the cache replacement policy implementation.
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2022-11-16 15:35:34 -06:00 |
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Ross Thompson
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d1ce84d172
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-16 12:44:06 -06:00 |
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Ross Thompson
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cf964e30fb
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-16 12:42:29 -06:00 |
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Ross Thompson
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5f7b0b8a9b
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Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
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2022-11-16 12:36:58 -06:00 |
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David Harris
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bc3b783543
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comment cleanup
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2022-11-16 10:23:20 -08:00 |
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David Harris
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ddba68605e
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Renamed DivBusy to FDivBusyE in FPU
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2022-11-16 10:13:27 -08:00 |
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David Harris
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e008d663f4
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Moved DivStartE to fdivsqrtfsm
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2022-11-16 10:00:07 -08:00 |
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Ross Thompson
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900a326a23
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Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
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2022-11-16 11:15:34 -06:00 |
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