212 Commits

Author	SHA1	Message	Date
David Harris	81ec1ac858	Separated out radix 2 and radix 4 stages into different modules	2022-08-29 04:26:14 -07:00
David Harris	b4cb9a678a	renamed srt to fdivsqrt	2022-08-29 04:04:05 -07:00
David Harris	35d0a951d2	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
David Harris	3959902c5b	Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus	2022-08-27 05:31:56 -07:00
David Harris	bd6f2444cd	Fixed address decoder hanging buildroot	2022-08-26 22:01:25 -07:00
Ross Thompson	4ad7ccc7f7	Possible fixes for earily messup of rv32ic and rv64ic configs.	2022-08-25 14:42:08 -05:00
Ross Thompson	5cc4f1f1cd	Added generate around uncore.	2022-08-25 10:35:24 -05:00
Ross Thompson	1e1646da90	Added generate around ebu.	2022-08-25 09:24:13 -05:00
Ross Thompson	22e989ac7b	No longer need wally-pipelined-fpga.do.	2022-08-24 18:10:45 -05:00
Ross Thompson	c636387613	Merged testbench-fpga into testbench. ... Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.	2022-08-24 17:52:25 -05:00
Ross Thompson	5301444a61	Changed signal names.	2022-08-17 16:12:04 -05:00
Katherine Parry	8eeca3319c	radix-2 1 copy passes testfloat	2022-08-06 22:54:05 +00:00
David Harris	6ee8036ae7	plic-s debug	2022-08-03 12:33:09 +00:00
Ross Thompson	acd920ae2f	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 22:09:11 -05:00
David Harris	e3b970d3ff	Partitioned fma into separate files	2022-08-01 18:07:38 +00:00
Ross Thompson	01359dbc4b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-31 12:48:51 -05:00
David Harris	449c80b5f7	More work toward riscof tests	2022-07-26 06:19:13 -07:00
David Harris	55ab81e37b	More riscof makefile tuning	2022-07-25 21:15:56 +00:00
David Harris	6b172723bd	Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings	2022-07-25 20:50:38 +00:00
Ross Thompson	334008630f	Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.	2022-07-24 01:20:29 -05:00
Ross Thompson	856ac24686	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
Ross Thompson	e12e6c3acd	Added more i-cache signals to wave file.	2022-07-24 00:24:13 -05:00
Ross Thompson	70032bf8f4	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-23 08:41:59 -05:00
Ross Thompson	0f586c9ed3	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Daniel Torres	b726b05d61	fixed wally rv32e tests, updated regression makefile to new testflow	2022-07-22 17:09:46 -07:00
Katherine Parry	ee7932c804	divider sizes reworked to match book	2022-07-22 22:02:04 +00:00
Katherine Parry	270216dd02	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
Ross Thompson	6c8ac7851e	Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.	2022-07-19 22:42:25 -05:00
Ross Thompson	ffda64587c	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
Katherine Parry	e599f82b29	moved Ss to execute stage	2022-07-18 20:48:56 +00:00
Katherine Parry	921debf930	removed underflow from inexactct calculation	2022-07-18 17:51:18 +00:00
Katherine Parry	e251022269	merged floating-point radix-2 divider with radix-4	2022-07-15 20:16:59 +00:00
Katherine Parry	b069cfbec2	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
Katherine Parry	e05b2a07d2	removed warnings and took a mux out of the critical path	2022-07-12 18:32:17 -07:00
Katherine Parry	2ada8a8bc1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-12 22:37:20 +00:00
Katherine Parry	b728e5054d	variable interations implemented in radix-4 divider	2022-07-11 18:30:21 -07:00
Katherine Parry	cd53ae67d9	moved fpu ieu write data mux to lsu	2022-07-08 23:56:57 +00:00
Katherine Parry	41c16be012	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
slmnemo	c5fd98ba99	sim-buildroot-batch now runs wally-pipelined-batch ... with option buildroot buildroot-no-trace to boot linux from step 0	2022-07-06 18:06:43 -07:00
David Harris	2b3038edf8	Added check to halt testbench on failing to find file	2022-07-05 02:28:59 +00:00
slmnemo	11956d0661	./regression-wally -buildroot or ./regression-wally -all now builds Linux from instruction 0 instead of trying to reach instruction 246000000	2022-06-29 13:40:11 -07:00
Katherine Parry	f25bb4a384	radix-4 early termination working for special cases - not working completely	2022-06-27 20:43:55 +00:00
Katherine Parry	c1b4e7fd2c	modified result select to account for x/inf	2022-06-24 21:23:15 +00:00
Katherine Parry	97ded2cdd9	div debug - accounted for 1 bit normalization in exponent calculation	2022-06-23 22:59:43 +00:00
Katherine Parry	5133b08161	generate qsel4 in verilog	2022-06-23 21:38:04 +00:00
slmnemo	a77fb485db	Added wally32periph to regression	2022-06-23 14:37:18 -07:00
Katherine Parry	4a6dee5926	Testfloat running division - not passing	2022-06-23 00:07:34 +00:00
slmnemo	10b6ff39a8	changed order of makefiles and fixed warnings when running makes	2022-06-21 16:10:18 -07:00
slmnemo	d291387b81	added individual makes for arch and wally tests as well as memfiles to Makefile. run using make archtests/wallytests/memfiles	2022-06-21 15:54:24 -07:00
Katherine Parry	c41391e228	removed rv64fp from lint	2022-06-21 15:48:47 -07:00