Kevin Kim
|
c694bde104
|
Merge branch 'main' of https://github.com/kipmacsaigoren/cvw
|
2023-02-03 18:39:26 +00:00 |
|
Kevin Kim
|
8c9107ffa4
|
arch32ba includes the 32i_m tests instead of 64
|
2023-02-03 17:40:02 +00:00 |
|
Kip Macsai-Goren
|
1096a4e2a5
|
Merge remote-tracking branch 'upstream/main' into main
|
2023-02-03 09:31:06 -08:00 |
|
Kevin Kim
|
c7ce9242cb
|
Merge branch 'main' of https://github.com/kipmacsaigoren/cvw
|
2023-02-03 16:00:36 +00:00 |
|
Kevin Kim
|
ac9e672e3e
|
ALU changes (ZBB)
- handles inverted operand instructions
- handles shift-and-add instructions
|
2023-02-03 16:00:32 +00:00 |
|
David Harris
|
02bdaf858c
|
Merge pull request #54 from ross144/main
Fixed issue #50, itlb and dcache flush interlock
|
2023-02-03 06:30:30 -08:00 |
|
Ross Thompson
|
370931c1cd
|
Fixed bug #49.
FFLAGS was updated while the pipeline was stalled.
Also I found serveral performance counters which had similar issues.
|
2023-02-03 00:39:26 -06:00 |
|
Ross Thompson
|
a4907b5d29
|
Lee Moore found another bug using imperas.
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
|
2023-02-02 23:52:21 -06:00 |
|
Kevin Kim
|
cb6e80a62b
|
Merge branch 'openhwgroup:main' into main
|
2023-02-02 21:41:55 -08:00 |
|
Kevin Kim
|
dd4f8c0712
|
Started Zbb
-Performs byte instructions (orc.b, rev8 (32/64))
|
2023-02-03 05:40:38 +00:00 |
|
Kevin Kim
|
ea98fdd7e4
|
zbs minor lint fix
|
2023-02-03 05:31:50 +00:00 |
|
Kevin Kim
|
441282f383
|
zbc initial done; passes lint.
clmul logic changes have not verified yet
|
2023-02-03 04:48:23 +00:00 |
|
Kevin Kim
|
34eb33a5e7
|
added bit reverse module, passes lint
|
2023-02-02 23:10:57 +00:00 |
|
David Harris
|
be618a0c34
|
Update README.md
|
2023-02-02 12:59:28 -08:00 |
|
Kevin Kim
|
1b6aca189d
|
started zbc
|
2023-02-02 20:11:11 +00:00 |
|
Kevin Kim
|
d498d2b2ff
|
zbs passes lint
|
2023-02-02 20:04:38 +00:00 |
|
James E. Stine
|
2a87495642
|
Merge pull request #52 from stineje/main
Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
|
2023-02-02 13:55:17 -06:00 |
|
James Stine
|
bfa69ea2b3
|
Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
|
2023-02-02 13:54:25 -06:00 |
|
Kevin Kim
|
c1ec17a7a6
|
clmul finished initial hdl; passes lint
|
2023-02-02 19:49:14 +00:00 |
|
David Harris
|
4c50166e56
|
Merge pull request #51 from stineje/main
Modify generic/mem for rv32gc ram2
|
2023-02-02 11:41:32 -08:00 |
|
James Stine
|
b66177fd87
|
Modify generic/mem for rv32gc ram2
|
2023-02-02 13:28:18 -06:00 |
|
Kevin Kim
|
655f5bbc5e
|
continued clmul unit
|
2023-02-02 18:54:33 +00:00 |
|
Kevin Kim
|
bdd12bfec6
|
started clmul
|
2023-02-02 16:40:58 +00:00 |
|
David Harris
|
bc0ca38b2f
|
Merge pull request #48 from ross144/main
Fixed bug #47, ecall and ebreak don't commit
|
2023-02-02 06:58:07 -08:00 |
|
Ross Thompson
|
091aadff0e
|
Merge branch 'main' of github.com:ross144/cvw
|
2023-02-02 08:52:48 -06:00 |
|
Ross Thompson
|
230888db8b
|
Fixed bug #47 discovered by Lee Moore.
ECALL and EBREAK do not commit their results.
|
2023-02-02 08:52:06 -06:00 |
|
Ross Thompson
|
d62a72a76f
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
|
2023-02-02 08:48:19 -06:00 |
|
Kip Macsai-Goren
|
0a6787026b
|
Merge remote-tracking branch 'upstream/main' into main
|
2023-02-01 21:31:57 -08:00 |
|
Kip Macsai-Goren
|
26e8b85111
|
added beginning of a ZBS instruction module to the ALU. Control signals still needed
|
2023-02-01 21:31:25 -08:00 |
|
Ross Thompson
|
a8afdf1741
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-02-01 19:24:10 -06:00 |
|
David Harris
|
c214a9e8fc
|
Merge pull request #45 from stineje/main
Update ram2 and other memories and associated wrappers
|
2023-02-01 15:06:30 -08:00 |
|
James Stine
|
6ce80b6b8a
|
Update ram2 and other memories and associated wrappers
|
2023-02-01 17:03:48 -06:00 |
|
Ross Thompson
|
0035579553
|
Minor branch predictor bug fix.
|
2023-02-01 10:59:38 -06:00 |
|
Ross Thompson
|
2a5b6408f2
|
Removed unused signal.
|
2023-02-01 10:27:58 -06:00 |
|
David Harris
|
73b29e1f71
|
Merge pull request #36 from davidharrishmc/dev
RV32imc configuration
|
2023-02-01 04:44:36 -08:00 |
|
David Harris
|
0280942563
|
Fixed merge conflict to get synthesis working again
|
2023-02-01 04:43:57 -08:00 |
|
David Harris
|
838bb21077
|
Merge pull request #43 from mmasserfrye/main
ram size, bpred size, memories *SYNTH NOT FUNCTIONAL*
|
2023-02-01 04:13:37 -08:00 |
|
Ross Thompson
|
c3e3afe398
|
Minor change to btb.
|
2023-02-01 00:24:54 -06:00 |
|
Madeleine Masser-Frye
|
ad6d7eb5e2
|
added memories (not tested)
|
2023-02-01 06:08:27 +00:00 |
|
Ross Thompson
|
a9624b1413
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-02-01 00:01:14 -06:00 |
|
Madeleine Masser-Frye
|
c78adbb8e7
|
increased bpred size to (2^) 5
|
2023-02-01 05:51:31 +00:00 |
|
Madeleine Masser-Frye
|
02a1432c46
|
updated synth makefile to change all relevant
ram ranges to 1FF
|
2023-02-01 05:40:35 +00:00 |
|
Madeleine Masser-Frye
|
a8ed39ecbe
|
Merge branch 'main' of https://github.com/mmasserfrye/cvw
|
2023-02-01 05:23:04 +00:00 |
|
Ross Thompson
|
8a6eaa23cc
|
Minor optimization to btb.
|
2023-01-31 22:03:51 -06:00 |
|
David Harris
|
c666015c56
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-01-31 14:40:19 -08:00 |
|
David Harris
|
9270285f3a
|
Removed student solution to fir
|
2023-01-31 14:40:12 -08:00 |
|
David Harris
|
8d242d47dd
|
Merge pull request #42 from ross144/main
Scripts to run imperas
|
2023-01-31 14:31:10 -08:00 |
|
Ross Thompson
|
81b280576f
|
Updates to RAS.
|
2023-01-31 15:17:32 -06:00 |
|
Ross Thompson
|
fc2e3fed91
|
Simplified RAS.
|
2023-01-31 14:54:05 -06:00 |
|
Ross Thompson
|
a89f9dc92c
|
RAS file name was spelled wrong.
|
2023-01-31 14:35:05 -06:00 |
|