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c666015c56
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413 Commits

Author SHA1 Message Date
David Harris
c666015c56 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-31 14:40:19 -08:00
Ross Thompson
c9c4f63c18 Fixed remaining bugs in the imperas merge. 2023-01-31 13:04:26 -06:00
Ross Thompson
026071e247 Merge branch 'imperas' 2023-01-31 12:46:22 -06:00
Ross Thompson
939095615f Fixed parameterization in testbench. 2023-01-31 00:11:01 -06:00
Ross Thompson
8feac6d242 Parameterized testbench branch predictor preload. 2023-01-31 00:08:11 -06:00
David Harris
a2f66313ea Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-30 11:00:51 -08:00
Ross Thompson
cc48cdc97b Imperas found a real bug in virtual memory. 
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.

Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
 2023-01-30 11:47:51 -06:00
David Harris
173c6b635c Moved WALLY-status-fp-enabled tests from a to priv suites 2023-01-29 17:19:53 -08:00
David Harris
e7883775f3 Moved shared constants into per-processor config and removed wally-constants 2023-01-29 15:55:37 -08:00
Ross Thompson
a9a7054e2f Merge branch 'main' of https://github.com/openhwgroup/cvw 
This merges the branch predictor improvements into the main repo.
 2023-01-29 15:24:20 -06:00
Ross Thompson
74b4f78099 Found bug in gshare. 2023-01-29 15:03:25 -06:00
Ross Thompson
e1fd5925b0 Fixed typo in testbench branch logger. 2023-01-29 01:00:52 -06:00
Ross Thompson
f62fbedbe8 Fixed another bug with the branch logger. 2023-01-29 00:59:59 -06:00
Ross Thompson
8e73f6b467 Fixed bug in the branch logger. 2023-01-29 00:58:50 -06:00
Ross Thompson
65a31381da Updated testbench for branch logger. 2023-01-29 00:56:11 -06:00
David Harris
94daedeed6 Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED 2023-01-28 18:52:00 -08:00
David Harris
e4e7e827d6 Renamed BUS to BUS_SUPPORTED 2023-01-28 18:35:53 -08:00
David Harris
a0b4e7fb24 Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED 2023-01-28 18:17:42 -08:00
Ross Thompson
6371d91b37 Added another performance counter to track overall branch miss-predictions. 2023-01-28 17:50:46 -06:00
David Harris
3906e706fd Removed integer from localparams 2023-01-27 14:40:06 -08:00
David Harris
3d13683c07 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
Ross Thompson
340e1797ea More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
5b5a615e4a Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
eroom1966
7c0cad148d Partial fix for misaligned LD/ST 2023-01-18 17:11:39 +00:00
eroom1966
2e4e5f9c61 changes made with Ross 2023-01-18 16:46:48 +00:00
eroom1966
df4419dea2 remove volatile for FFLAGS and FCSR 2023-01-18 13:33:57 +00:00
Ross Thompson
b30c13a188 Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage. 2023-01-17 18:24:46 -06:00
Ross Thompson
aa942feedc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-17 15:44:44 -06:00
David Harris
c73bea83cd Clean up warnings from Questa 2023-01-17 13:43:39 -08:00
Ross Thompson
caff6e788c Somehow the imperas files spilled into the main branch. 2023-01-17 15:39:34 -06:00
eroom1966
8caa93ce4d refactor all rvvi into single initial block 2023-01-17 13:01:01 +00:00
eroom1966
f4e7e54abe Code refactor and addition of rvvi interface 2023-01-17 12:47:38 +00:00
Ross Thompson
fabe13bdce Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs. 2023-01-16 13:35:06 -06:00
David Harris
efe7e88258 csr cleanup 2023-01-13 22:12:06 -08:00
David Harris
9526479782 csr cleanup 2023-01-13 21:25:55 -08:00
Ross Thompson
76a9e7d963 Merge branch 'rastemp' 2023-01-13 18:09:50 -06:00
Ross Thompson
cf608ee45f Possible optimization of gshare. 
I don't believe the Writeback stage ghr is needed.
 2023-01-13 12:39:29 -06:00
Ross Thompson
395b7a5b32 Nearly complete RVVI tracer. 
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
 2023-01-12 18:43:39 -06:00
Ross Thompson
ef4c684336 Added supervisor mode registers to tracer. 2023-01-12 17:04:41 -06:00
Ross Thompson
9917be817c Added M CSRs to the CSRArray. 2023-01-12 16:51:51 -06:00
Ross Thompson
a68773eba1 added machine csr to logger. 2023-01-12 16:35:19 -06:00
Ross Thompson
2e622c9860 Added support to print the gprs. 2023-01-12 16:09:30 -06:00
Ross Thompson
4733b787f8 rvvi trace is coming alone nicely. 2023-01-12 14:46:31 -06:00
Ross Thompson
3cc37e3f12 Completely stripped down imperas simulation. 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
 2023-01-12 12:48:38 -06:00
Ross Thompson
2f2f3d6da5 Stripped out all signature checking. 
Removed multiple tests loop.
Only runs 1 test now.
 2023-01-12 12:45:44 -06:00
Ross Thompson
5ad0bacf5b Created separate imperas testbench. 
Resolved logger issue with the duplicated instructions after commit.
 2023-01-12 12:07:07 -06:00
Ross Thompson
94f24d3f58 Added instruction logger. 2023-01-12 10:09:34 -06:00
Katherine Parry
77a982c977 cleaned up all FPU files except for division 2023-01-11 22:02:30 -06:00
Ross Thompson
6a616617d1 Restored to default configuration. 2023-01-09 00:21:45 -06:00
Ross Thompson
bf08c57ab0 Added branch outcome logger to testbench 2023-01-07 13:16:57 -06:00