Ross Thompson 3cc37e3f12 Completely stripped down imperas simulation. ... run with vsim -c -do "do wally-pipelined-imperas.do rv64gc"		2023-01-12 12:48:38 -06:00
..
common	Added WFI to the testbench instruction name decoder	2022-04-14 17:12:11 +00:00
fp	Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."	2022-12-04 00:01:58 +00:00
sdc	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
testbench_imperas.sv	Completely stripped down imperas simulation.	2023-01-12 12:48:38 -06:00
testbench-fp.sv	some commenting fixes, converter optimizations, and moves normshift into postproc	2023-01-03 15:55:30 -06:00
testbench-linux.sv	Renamed signals in the LSU.	2022-09-13 11:47:39 -05:00
testbench.sv	Added instruction logger.	2023-01-12 10:09:34 -06:00
tests-fp.vh	postprocessing unit created and passing all tests	2022-06-13 22:47:51 +00:00
tests.vh	Simiplified global history branch predictor.	2023-01-04 23:41:55 -06:00