ushakya22
fd5a1f3874
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-07 04:06:54 -04:00
Domenico Ottolia
60cf38192b
Add privileged tests to testbench
2021-04-07 02:22:08 -04:00
Domenico Ottolia
465d3986b0
Add passing mtval and mepc tests
2021-04-07 02:21:05 -04:00
Ross Thompson
c91436d3b7
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Ross Thompson
98a04abe6c
Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
2021-04-06 21:20:55 -05:00
Ross Thompson
bff2d61a1f
Steps to getting branch predictor benchmarks running.
2021-04-06 21:20:51 -05:00
Jarred Allen
bd8f1eea3c
Fix another bug in icache
2021-04-06 17:47:00 -04:00
Jarred Allen
3afc358974
Fix another bug in icache
2021-04-06 12:48:42 -04:00
ushakya22
4ac4cf2aaa
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-06 12:29:23 -04:00
Noah Boorstin
284d583877
add busybear boot files with git-lfs
2021-04-05 19:38:43 -04:00
Noah Boorstin
0e3f013212
busybear: reenable 'ruthless' CSR checking
2021-04-05 12:53:30 -04:00
bbracker
38017e6aae
declare memread signal
2021-04-05 08:13:01 -04:00
bbracker
a4c3afb847
PLIC claim reg side effects now check for memread signal
2021-04-05 08:03:14 -04:00
bbracker
4a5aa5b202
plic subword access compliance
2021-04-04 23:10:33 -04:00
Katherine Parry
e6a7353847
Added missing files in FPU
2021-04-04 18:09:13 +00:00
bbracker
31c6b2d01f
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Thomas Fleming
6b43381c38
Comment out fpu from hart until module exists
2021-04-03 22:34:11 -04:00
Thomas Fleming
dbd5a4320e
Merge branch 'mmu' into main
...
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
2021-04-03 22:12:52 -04:00
Thomas Fleming
8dfec29f7e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-03 22:09:50 -04:00
Noah Boorstin
f4e5642c62
busybear: temporary stop after 800k instrs
2021-04-03 21:37:57 -04:00
Thomas Fleming
1cbdaf1f05
Fix extraneous page fault stall
2021-04-03 21:28:24 -04:00
Thomas Fleming
6a35308068
Virtual memory test now turns on virtual memory
2021-04-03 21:24:06 -04:00
Jarred Allen
c95da7d11e
Fix bug in icache
2021-04-03 18:10:54 -04:00
Katherine Parry
d7b1379ab8
Integrated FPU
2021-04-03 20:52:26 +00:00
Ross Thompson
d21006d048
Partial fix to the integer divide stall issue.
2021-04-02 15:32:15 -05:00
James E. Stine
362f6ea2e6
Minor cleanup
2021-04-02 08:20:44 -05:00
James E. Stine
0595ae983f
Put back imperas testbench until figure out why m_supported is running for rv64ic
2021-04-02 08:19:25 -05:00
James E. Stine
cff08adc3a
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
2021-04-02 06:27:37 -05:00
Thomas Fleming
bfb4b051c6
Merge branch 'main' into mmu
2021-04-01 16:29:39 -04:00
Thomas Fleming
350fe87119
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-01 16:24:06 -04:00
Thomas Fleming
38a0199260
Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu
2021-04-01 16:23:19 -04:00
Thomas Fleming
fdb20ee1cf
Implement sfence.vma and fix tlb writing
2021-04-01 15:55:05 -04:00
ushakya22
498433f8bf
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-01 15:49:00 -04:00
Jarred Allen
5afb255251
Begin changes to direct-mapped cache
2021-04-01 13:55:21 -04:00
Shreya Sanghai
df149d1be7
fixed minor bugs in localHistory
2021-04-01 13:40:08 -04:00
James E. Stine
0495195d68
Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time.
2021-04-01 12:30:37 -05:00
ShreyaSanghai
28a9c6ba56
added localHistoryPredictor
2021-04-01 22:22:40 +05:30
ushakya22
ee89b891a4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-01 02:04:57 -04:00
ushakya22
bee984a126
d
2021-04-01 02:04:02 -04:00
Shreya Sanghai
b544526766
fixed bugs in global history to read latest GHRE
2021-03-31 21:56:14 -04:00
Teo Ene
7c364a26e9
Updated MISA in coremark_bare config file
2021-03-31 20:39:02 -05:00
Noah Boorstin
75f58c4df5
busybear: temporarially stop checking CSRs
2021-03-31 14:14:32 -04:00
Noah Boorstin
118e846ef7
busybear: clean up questa warnings
2021-03-31 14:04:57 -04:00
Noah Boorstin
43532be770
busybear: clean up questa warnings
2021-03-31 14:02:15 -04:00
Ross Thompson
9172e52286
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Ross Thompson
a64a37d702
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Thomas Fleming
853ddeba15
Remove virtual memory tests from rv32i folder
2021-03-30 22:51:52 -04:00
Thomas Fleming
77b8e27205
Disable 'always-on' virtual memory
2021-03-30 22:49:47 -04:00
Thomas Fleming
56e256baa5
Extend lint-wally to lint both rv32 and rv64
2021-03-30 22:42:28 -04:00
Thomas Fleming
eca2427f94
Merge remote-tracking branch 'origin/main' into main
...
Bring icache and MMU code together
Conflicts:
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 22:24:47 -04:00
