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265 Commits

Author SHA1 Message Date
David Harris
2cea3349ad LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
David Harris
6431ad4a8b Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
David Harris
8e83aaeced fma file fixes 2022-03-02 23:47:01 +00:00
bbracker
11423d1d17 but apparently QEMU doesn't show UXL in SSTATUS 2022-03-02 22:44:19 +00:00
bbracker
6d7bc928af update SXL UXL bits in MSTATUS to match new QEMU trace 2022-03-02 22:15:57 +00:00
David Harris
c543fedc60 removed imperas-riscv-tests 2022-03-02 17:28:20 +00:00
David Harris
0ecfff7e3a FMA project ready to start 2022-03-01 20:58:08 +00:00
David Harris
329fea9329 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
David Harris
2ea93c4ac3 adrdecs comments 2022-02-28 20:33:41 +00:00
David Harris
2de31a15da Modified address decoder for native access to CLINT 2022-02-28 19:13:14 +00:00
David Harris
3a43450ac9 hptw cleanup for synthesis 2022-02-28 05:54:34 +00:00
David Harris
f4be78ecc3 Created softfloat_demo showcasing how to do math with SoftFloat 2022-02-27 18:17:21 +00:00
David Harris
3675a813c6 Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior 2022-02-27 17:23:33 +00:00
David Harris
62d62f9a9e Moved FMA back into source tree to facilitate synthesis 2022-02-27 15:41:41 +00:00
David Harris
c35a071203 Moved fma directory 2022-02-27 14:20:15 +00:00
David Harris
283a25e1a7 fma simulation infrastructure 2022-02-27 04:36:43 +00:00
David Harris
40bc380073 fma passing multiply vectors 2022-02-27 04:36:01 +00:00
David Harris
f29cc4b33f simplified fma Makefile 2022-02-26 19:55:42 +00:00
David Harris
b2db58e982 Made softfloat.a a symlink 2022-02-26 19:53:04 +00:00
David Harris
a9f9cfa5b6 Added start of fma 2022-02-26 19:51:19 +00:00
Ross Thompson
730fdb029a Fixed bug with DAPageFault being wrong when HPTW writes not supported. 2022-02-23 10:54:34 -06:00
Ross Thompson
6f53f7943f More spillsupport more structual. 2022-02-23 10:27:14 -06:00
Ross Thompson
19ec874641 Fixed bug with spill support and Instruction DA Page Faults. 2022-02-23 10:16:12 -06:00
Ross Thompson
15f6871a8d Added generates to pcnextf muxes for privileged and caches. 2022-02-22 22:45:00 -06:00
Ross Thompson
59f04f2518 Minor busdp cleanup. 2022-02-22 17:28:26 -06:00
Ross Thompson
ea29291024 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-22 14:45:53 -06:00
Ross Thompson
971dd494f6 Clarified interlockfsm. 2022-02-22 11:31:28 -06:00
bbracker
2322e66f9f fix lint bugs in PLIC and UART 2022-02-22 05:04:18 +00:00
bbracker
ac114e1c6d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-22 04:27:50 +00:00
bbracker
c26526c9f3 change RX side of UART to aslo be LSB-first 2022-02-22 03:34:08 +00:00
Ross Thompson
1ab2e7590b Added some clearity to lsuvirtmem.sv. 2022-02-21 17:20:58 -06:00
Ross Thompson
8a280f211f Annotated IFU for mux changes. 2022-02-21 17:20:34 -06:00
Ross Thompson
ace743ae91 Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW. 2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9 Cleaned up names in lsuvirtmem. 2022-02-21 16:44:30 -06:00
Ross Thompson
456a54166a Minor cleanup of lsu. 2022-02-21 12:46:06 -06:00
Ross Thompson
5d9ad011d2 Moved mux into lsuvirtmem. 2022-02-21 09:31:29 -06:00
Ross Thompson
8af055c78e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-21 09:06:09 -06:00
Ross Thompson
a60332b455 Minor changes to LSU. 2022-02-19 14:38:17 -06:00
David Harris
4e194b2576 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7 Removed problematic warning about reaching default state in HPTW 2022-02-18 23:08:40 +00:00
Ross Thompson
0bd533473c New config option to enable hptw writes to PTE in memory to update Access and Dirty bits. 2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453 Accidentally cleared dirty bit when setting access bit in hptw. 2022-02-17 16:20:20 -06:00
Ross Thompson
7dffcba182 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-17 14:49:37 -06:00
Ross Thompson
d152733a17 Rough implementation passing regression test with hptw atomic writes to memory. 2022-02-17 14:46:11 -06:00
David Harris
3036de316a Started make allsynth to try many experiments 2022-02-17 17:57:02 +00:00
Ross Thompson
4cfb601dc8 Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB. 2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3 Broken state. address translation not working after changes to hptw to support atomic updates to PT. 2022-02-16 23:37:36 -06:00
Ross Thompson
beac362364 Moved a few muxes around after sww changes. 2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01 cleanup of signal names. 2022-02-16 15:29:08 -06:00
Ross Thompson
84edb8b5d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 15:22:35 -06:00