Ross Thompson
bff2d61a1f
Steps to getting branch predictor benchmarks running.
2021-04-06 21:20:51 -05:00
Ross Thompson
9172e52286
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Ross Thompson
2a308309e4
fixed some bugs with the RAS.
2021-03-30 13:57:40 -05:00
Ross Thompson
a99c0502e5
Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
2021-03-24 15:56:55 -05:00
Ross Thompson
11109e5a88
Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed.
2021-03-24 13:03:43 -05:00
Ross Thompson
d74b6eb69c
Updated the .gitignore to reject all the extra compiled objects for the branchmarks.
2021-03-24 10:30:19 -05:00
Ross Thompson
efa8ad4e17
Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack.
2021-03-24 09:22:21 -05:00
Ross Thompson
1c6e37120e
Fixed RAS errors. Still some room for improvement with the BTB and RAS.
2021-03-23 23:00:44 -05:00
Ross Thompson
84ad1353e4
Fixed a bunch of bugs with the RAS.
2021-03-23 21:49:16 -05:00
Ross Thompson
4fb7a1e0a6
Fixed the valid bit issue. Now the branch predictor is actually predicting instructions.
2021-03-23 20:20:23 -05:00
Ross Thompson
49348d734b
fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
2021-03-23 20:06:45 -05:00
Ross Thompson
95dbc5f1fa
fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.
2021-03-23 16:53:48 -05:00
Ross Thompson
174557ae89
Simulation definitely shows the branch predictor counters and branch predictor don't work. :(
2021-03-23 14:04:58 -05:00
Ross Thompson
5edc90b1c2
added a whole bunch of interseting test code for branches which does not work.
2021-03-23 13:54:59 -05:00
Ross Thompson
6a050219d4
updated the branch predictor config.
2021-03-23 13:54:59 -05:00
Ross Thompson
9e61481414
Added first benchmark.
2021-03-23 13:54:59 -05:00
Ross Thompson
2b0f7cdd42
Temporary exe2memfile0.pl script to support starting addresses of 0.
2021-03-23 13:54:59 -05:00
Ross Thompson
e1842c8da6
Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.
2021-03-23 13:54:59 -05:00
Shreya Sanghai
1d6a2989ed
PC counts branch instructions
2021-03-23 14:25:51 -04:00
Jarred Allen
7da8af4c68
Another tweak to regression-wally.py comments
2021-03-23 00:18:38 -04:00
Jarred Allen
82de84469f
Slight change to regression-wally.py comments
2021-03-23 00:02:40 -04:00
Noah Boorstin
849641f31e
busybear: add better warning on illegal instruction
...
...also it seems that mret is being picked up as an illegal instruction??
2021-03-22 18:24:35 -04:00
Noah Boorstin
34b8f750ce
busybear: temporarially force rf[5] correct after failure to read CSR
2021-03-22 18:12:41 -04:00
Noah Boorstin
77dd0b4504
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
Noah Boorstin
7bb31c3287
busybear: finally get the right error
2021-03-22 16:52:22 -04:00
bbracker
5efd5958e7
added delays to uart AHB signals
2021-03-22 15:40:29 -04:00
Noah Boorstin
2aa76b27e1
busybear: comment out some debug printing
2021-03-22 14:54:05 -04:00
Noah Boorstin
74bcd9b994
regression: expect 200k instead of 100k busybear instrs
...
and a minor busybear bugfix
2021-03-22 14:47:52 -04:00
bbracker
11d4a8ab34
first pass at PLIC interface
2021-03-22 10:14:21 -04:00
Katherine Parry
f741ba7702
fixed various bugs in the FMA
2021-03-21 22:53:04 +00:00
Katherine Parry
e317e7511e
messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic
2021-03-20 02:05:16 +00:00
bbracker
85363e941d
AHB bugfixes and sim waveview refactoring
2021-03-18 18:25:12 -04:00
Shreya Sanghai
09faa40eb6
fixed minor bugs in testbench
2021-03-18 17:37:10 -04:00
Shreya Sanghai
bbe0957df5
Merge branch 'gshare' into main
...
Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1
Switched to gshare from global history.
...
Fixed a few minor bugs.
2021-03-18 16:05:59 -05:00
Ross Thompson
8f4051543c
Fixed minor bug with the size of gshare.
2021-03-18 16:00:09 -05:00
Shreya Sanghai
eb86bfc084
removed unnecesary PC registers in ifu
2021-03-18 16:31:21 -04:00
Thomas Fleming
8d484174a7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-18 14:36:42 -04:00
Thomas Fleming
7f7597e667
Connect tlb, pagetablewalker, and memory
2021-03-18 14:35:46 -04:00
Thomas Fleming
7d4906b1c7
Improve page table creation in python file
2021-03-18 14:27:09 -04:00
Noah Boorstin
bc1a0c6ee7
change ifndef to generate/if
2021-03-18 12:50:19 -04:00
Noah Boorstin
a2b0af460e
everyone gets a bootram
2021-03-18 12:35:37 -04:00
Noah Boorstin
ced2a32d21
busybear: update memory map, add GPIO
2021-03-18 12:17:35 -04:00
Teo Ene
57f1ca5259
Switched coremark to RV64IM
2021-03-17 22:39:56 -05:00
Teo Ene
d2fe42d6d0
adapted coremark bare testbench to new dtim RAM HDL
2021-03-17 16:59:02 -05:00
Teo Ene
4fd0ecff69
Temporarily reverted my last few commits
2021-03-17 15:16:01 -05:00
Teo Ene
7446a7b479
fix to last commit
2021-03-17 15:07:02 -05:00
Teo Ene
3e849f99a6
fix to last commit
2021-03-17 15:02:15 -05:00
Teo Ene
d72d774a0b
addition to last commit
2021-03-17 14:52:31 -05:00
Teo Ene
dfe6df2e00
Added Ross's addr lab stuff to coremark stuff
2021-03-17 14:50:54 -05:00
