bbracker
3565580f40
updated buildroot make procedure to incorporate configs more robustly
2021-07-13 12:40:14 -04:00
Ross Thompson
224e3b2991
Fixed subword write. subword read should not feed into subword write.
2021-07-13 11:21:44 -05:00
Ross Thompson
30b7c4436c
restored rv64ic config back to full sized dtim.
2021-07-13 11:18:54 -05:00
Ross Thompson
3951eb56f5
Modularized the shadow memory to reduce performance hit.
2021-07-13 10:55:57 -05:00
Ross Thompson
e594eb540d
Got the shadow ram cache flush working.
2021-07-13 10:03:47 -05:00
bbracker
99587f58f7
whoops I accidentally made main.config into a symbolic link; now it is a source file
2021-07-13 11:00:01 -04:00
bbracker
fab906821a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 10:04:13 -04:00
bbracker
4b615c1564
working config for a buildroot that boots
2021-07-13 10:04:09 -04:00
David Harris
861ef5e1cb
Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
2021-07-13 09:32:02 -04:00
Ross Thompson
49f6eec579
Team work on solving the dcache data inconsistency problem.
2021-07-12 23:46:32 -05:00
Ross Thompson
ecc9b5006e
Now updates the dtim with the dirty data in the dcache.
...
Simulation is showing issues. It lookslike the cache is not
evicting the correct data.
2021-07-12 15:13:27 -05:00
Ross Thompson
1cc258ade1
Progress towards the test bench flush.
2021-07-12 14:22:13 -05:00
Katherine Parry
f3ac46df86
fcvt.sv cleanup
2021-07-11 21:30:01 -04:00
Katherine Parry
36f59f3c99
Almost all convert instructions pass Imperas tests
2021-07-11 18:06:33 -04:00
bbracker
6bd0ca673c
rootfs.cpio no longer overlaps
2021-07-11 05:11:12 -04:00
Ross Thompson
f26d635614
Fixed the spurious AHB requests to address 0. Somehow by not having a default
...
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
2021-07-10 22:34:47 -05:00
Ross Thompson
fed7042fd9
Loads are working.
...
There is a bug when the icache stalls 1 cycle before the d cache.
2021-07-10 22:15:44 -05:00
Ross Thompson
60ed023734
Actually writes the correct data now on stores.
2021-07-10 17:48:47 -05:00
Ross Thompson
efe37ea079
Write miss with eviction works.
2021-07-10 15:17:40 -05:00
Ross Thompson
d65c01bc29
Write Hits and Write Misses without eviction are working correctly! The next
...
step is to add eviction of dirty lines.
2021-07-10 10:56:25 -05:00
bbracker
feaeeaf6ac
greatly stripped down unused stuff in linux config
2021-07-10 11:53:35 -04:00
David Harris
20f2a4e47c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 19:18:35 -04:00
David Harris
d3ab6b192a
added missing tlbmixer.sv
2021-07-09 19:18:23 -04:00
bbracker
3be73695e3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 18:56:28 -04:00
bbracker
2a54f6f242
fix_mem.py bugfix
2021-07-09 18:56:17 -04:00
Ross Thompson
b1ceeb40df
Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address.
...
I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
2021-07-09 17:14:54 -05:00
bbracker
1f52a2f938
organize/update buildroot scripts for new image
2021-07-09 17:03:47 -04:00
Ross Thompson
4c0cee1c19
Design loads in modelsim, but trap is an X.
2021-07-09 15:37:16 -05:00
Ross Thompson
ec80cc1820
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
...
Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
David Harris
39bd7e7edc
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 07:53:30 -04:00
David Harris
5c2f774c35
Simplified tlbmixer mux to and-or
2021-07-08 23:34:24 -04:00
David Harris
74b6d13195
Fixed missing stall in InstrRet counter
2021-07-08 20:08:04 -04:00
bbracker
44a48cf28d
organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files
2021-07-08 19:18:11 -04:00
Ross Thompson
94c3fde724
Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache.
2021-07-08 18:03:52 -05:00
Ross Thompson
93aa39ca31
completed read miss branch through dcache fsm.
...
The challenge now is to connect to ahb and lsu.
2021-07-08 17:53:08 -05:00
David Harris
4f1a85ca7c
Eliminate reserved bits from TLB RAM
2021-07-08 17:35:00 -04:00
David Harris
38772de21f
Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
2021-07-08 16:58:11 -04:00
David Harris
1190729896
TLB cleanup to match diagrams
2021-07-08 16:52:06 -04:00
Ross Thompson
910ddb83ae
This d cache fsm is getting complex.
2021-07-08 15:26:16 -05:00
Ross Thompson
1fe06bc670
Partial implementation of the data cache. Missing the fsm.
2021-07-07 17:52:16 -05:00
David Harris
5d5274ec73
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-07 06:32:29 -04:00
David Harris
2bab3f769b
Renamed tlb ReadLines to Matches
2021-07-07 06:32:26 -04:00
Abe
84711fbdc8
Updated MISA defining as well as porting sizes for peripherals (34 to 56)
2021-07-07 02:37:09 -04:00
Abe
c721341691
Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time.
2021-07-07 02:28:11 -04:00
Abe
b536065ee8
Removed debugging loop to test timers for clarity
2021-07-06 23:37:43 -04:00
Abe
8dc40e988e
Updated portme file to include counters MTIME and MINSTRET. Timer currently set to read milliseconds running at 100MHZ, but this can be changed by setting a different clock speed in the testbench sv file and manipulating TIMER_RES_DIVIDER on line 120
2021-07-06 23:35:47 -04:00
Abe
b757c96b2d
Changed SvMode to SVMode on line 76
2021-07-06 23:28:58 -04:00
David Harris
af619dcd75
Added ASID matching for CAM
2021-07-06 18:56:25 -04:00
Kip Macsai-Goren
8350622f65
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-06 18:54:41 -04:00
David Harris
7d857cf4bd
more TLB name touchups
2021-07-06 18:39:30 -04:00
