Ross Thompson
a973681a90
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
aad28366d7
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
David Harris
602867f54e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-13 21:46:00 +00:00
David Harris
7d13740a11
Mixed C and assembly language test cases; SRT initial version passing tests
2022-01-13 21:45:54 +00:00
Ross Thompson
e6e3b0607a
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
f870b8b3d3
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
Ross Thompson
66f3259984
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
a23e6efd5c
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
85b5dc08a8
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
e06fb923a1
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
e5262b80a6
Merge branch 'testDivInterruptInterlock' of github.com:davidharrishmc/riscv-wally into testDivInterruptInterlock
2022-01-12 14:17:49 -06:00
Ross Thompson
11f1613d59
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
d8173745bb
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
cd75bf98e1
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
b294f1fbb0
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-12 14:17:16 -06:00
Ross Thompson
459f4bd3b4
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
960af4b70f
Set rv32ic to not use icache.
2022-01-12 14:10:09 -06:00
Ross Thompson
f18684efbf
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-12 13:29:19 -06:00
Ross Thompson
786a772444
Improve wavefile by adding performance counters.
2022-01-12 10:53:29 -06:00
David Harris
4b7ee9815e
C sum example
2022-01-12 09:04:41 +00:00
James E. Stine
f91b635652
remove extraneous
2022-01-11 16:01:48 -06:00
James E. Stine
14e53099f8
Update on assembly simple/spike
2022-01-11 15:59:56 -06:00
David Harris
10921accdb
Added inline assembly to simple
2022-01-11 21:32:30 +00:00
David Harris
02f6030c02
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-11 21:01:50 +00:00
David Harris
486cfdc3a5
Added C test cases
2022-01-11 21:01:48 +00:00
Kip Macsai-Goren
c251144460
Fixed PMA regions, Added passing PMA tests to regression
2022-01-10 22:08:26 +00:00
David Harris
0b3d3b768b
Do file for riscvsingle
2022-01-10 16:26:18 +00:00
David Harris
86857a877b
Added fulladder example files
2022-01-10 16:15:05 +00:00
David Harris
3a2b459439
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
401a5b1779
Removed unused coremark_bare
2022-01-10 05:05:55 +00:00
David Harris
39d5570d2c
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
04ea93aa27
Added performance counters to wavefile.
2022-01-09 22:42:14 -06:00
Ross Thompson
ae927e2bc6
Fixed wavefile.
...
Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
Ross Thompson
3447c23d9b
Added additional fsm to ILA.
2022-01-09 17:10:57 -06:00
Ross Thompson
fbff9edc8f
Possible fix for the TrapM DTLBMiss suppression.
2022-01-09 14:22:14 -06:00
Kip Macsai-Goren
54aab6cdde
comment cleanup
2022-01-09 18:16:42 +00:00
Kip Macsai-Goren
53ea1360ce
updated PMA tests, everything passes except successful writes to protected regions.
2022-01-09 18:16:00 +00:00
Kip Macsai-Goren
5f7323f25f
changed test case types to lookup table instead of beq's
2022-01-09 16:56:37 +00:00
David Harris
0212260eef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-09 14:39:33 +00:00
David Harris
c1d2199dc6
Fixed RISCV path in coremark Makefile
2022-01-09 14:39:22 +00:00
Ross Thompson
8fb5500be8
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-08 20:49:45 -06:00
Ross Thompson
c7c8b128b3
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-08 17:21:27 -06:00
Ross Thompson
aa59dfa095
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-08 14:21:58 -06:00
Ross Thompson
d14dffd010
Updated debug constraints again to match changes in verilog.
2022-01-08 13:28:51 -06:00
Ross Thompson
0f14d2ec88
Added advanced Vivado debug scripts.
2022-01-07 17:56:40 -06:00
Ross Thompson
509a0cd3f8
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
54d852f6ae
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
bea6d0856d
Testbench directory cleanup
2022-01-07 17:02:16 +00:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
