Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
2,460 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
7d13740a11
Go to file
David Harris 7d13740a11 Mixed C and assembly language test cases; SRT initial version passing tests
2022-01-13 21:45:54 +00:00
addins Added C test cases 2022-01-11 21:01:48 +00:00
benchmarks/riscv-coremark Merged coremark changes 2022-01-10 05:09:28 +00:00
bin Code cleanup 2022-01-07 04:07:04 +00:00
examples Mixed C and assembly language test cases; SRT initial version passing tests 2022-01-13 21:45:54 +00:00
fpga Updated debug constraints again to match changes in verilog. 2022-01-08 13:28:51 -06:00
pipelined Mixed C and assembly language test cases; SRT initial version passing tests 2022-01-13 21:45:54 +00:00
tests Fixed PMA regions, Added passing PMA tests to regression 2022-01-10 22:08:26 +00:00
.gitattributes Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
.gitignore Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
.gitmodules Added C test cases 2022-01-11 21:01:48 +00:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
Makefile Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
README.md Update README.md 2022-01-05 11:29:54 -08:00
setup.sh Code cleanup 2022-01-07 04:07:04 +00:00
wallyVirtIO.patch added wallyVirtIO.patch from Ross 2021-12-22 07:04:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

See Chapter 2 of draft book of how to install and compile tests.