Ross Thompson
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a4907b5d29
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Lee Moore found another bug using imperas.
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
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2023-02-02 23:52:21 -06:00 |
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David Harris
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be618a0c34
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Update README.md
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2023-02-02 12:59:28 -08:00 |
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James E. Stine
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2a87495642
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Merge pull request #52 from stineje/main
Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
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2023-02-02 13:55:17 -06:00 |
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James Stine
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bfa69ea2b3
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Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
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2023-02-02 13:54:25 -06:00 |
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David Harris
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4c50166e56
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Merge pull request #51 from stineje/main
Modify generic/mem for rv32gc ram2
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2023-02-02 11:41:32 -08:00 |
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James Stine
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b66177fd87
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Modify generic/mem for rv32gc ram2
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2023-02-02 13:28:18 -06:00 |
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David Harris
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bc0ca38b2f
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Merge pull request #48 from ross144/main
Fixed bug #47, ecall and ebreak don't commit
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2023-02-02 06:58:07 -08:00 |
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Ross Thompson
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091aadff0e
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Merge branch 'main' of github.com:ross144/cvw
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2023-02-02 08:52:48 -06:00 |
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Ross Thompson
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230888db8b
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Fixed bug #47 discovered by Lee Moore.
ECALL and EBREAK do not commit their results.
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2023-02-02 08:52:06 -06:00 |
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Ross Thompson
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d62a72a76f
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2023-02-02 08:48:19 -06:00 |
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Ross Thompson
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a8afdf1741
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-01 19:24:10 -06:00 |
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David Harris
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c214a9e8fc
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Merge pull request #45 from stineje/main
Update ram2 and other memories and associated wrappers
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2023-02-01 15:06:30 -08:00 |
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James Stine
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6ce80b6b8a
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Update ram2 and other memories and associated wrappers
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2023-02-01 17:03:48 -06:00 |
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Ross Thompson
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0035579553
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Minor branch predictor bug fix.
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2023-02-01 10:59:38 -06:00 |
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Ross Thompson
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2a5b6408f2
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Removed unused signal.
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2023-02-01 10:27:58 -06:00 |
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David Harris
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73b29e1f71
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Merge pull request #36 from davidharrishmc/dev
RV32imc configuration
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2023-02-01 04:44:36 -08:00 |
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David Harris
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0280942563
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Fixed merge conflict to get synthesis working again
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2023-02-01 04:43:57 -08:00 |
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David Harris
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838bb21077
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Merge pull request #43 from mmasserfrye/main
ram size, bpred size, memories *SYNTH NOT FUNCTIONAL*
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2023-02-01 04:13:37 -08:00 |
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Ross Thompson
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c3e3afe398
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Minor change to btb.
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2023-02-01 00:24:54 -06:00 |
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Madeleine Masser-Frye
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ad6d7eb5e2
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added memories (not tested)
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2023-02-01 06:08:27 +00:00 |
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Ross Thompson
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a9624b1413
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-01 00:01:14 -06:00 |
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Madeleine Masser-Frye
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c78adbb8e7
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increased bpred size to (2^) 5
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2023-02-01 05:51:31 +00:00 |
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Madeleine Masser-Frye
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02a1432c46
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updated synth makefile to change all relevant
ram ranges to 1FF
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2023-02-01 05:40:35 +00:00 |
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Madeleine Masser-Frye
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a8ed39ecbe
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Merge branch 'main' of https://github.com/mmasserfrye/cvw
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2023-02-01 05:23:04 +00:00 |
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Ross Thompson
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8a6eaa23cc
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Minor optimization to btb.
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2023-01-31 22:03:51 -06:00 |
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David Harris
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c666015c56
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-01-31 14:40:19 -08:00 |
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David Harris
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9270285f3a
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Removed student solution to fir
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2023-01-31 14:40:12 -08:00 |
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David Harris
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8d242d47dd
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Merge pull request #42 from ross144/main
Scripts to run imperas
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2023-01-31 14:31:10 -08:00 |
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Ross Thompson
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81b280576f
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Updates to RAS.
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2023-01-31 15:17:32 -06:00 |
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Ross Thompson
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fc2e3fed91
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Simplified RAS.
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2023-01-31 14:54:05 -06:00 |
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Ross Thompson
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a89f9dc92c
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RAS file name was spelled wrong.
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2023-01-31 14:35:05 -06:00 |
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Ross Thompson
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92fc532b82
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Created scripts to install imperas and run a single test using imperas.
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2023-01-31 13:51:05 -06:00 |
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David Harris
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ce98083ffd
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Merge pull request #41 from ross144/main
Merged imperas branch into main. Remove old branch when pull request accepted.
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2023-01-31 11:35:50 -08:00 |
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Ross Thompson
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d821105697
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-01-31 13:04:41 -06:00 |
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Ross Thompson
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c9c4f63c18
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Fixed remaining bugs in the imperas merge.
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2023-01-31 13:04:26 -06:00 |
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Ross Thompson
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026071e247
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Merge branch 'imperas'
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2023-01-31 12:46:22 -06:00 |
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Ross Thompson
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5a770f148c
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Minor bug fix in gshare.
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2023-01-31 10:45:32 -06:00 |
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Ross Thompson
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ad0a0f0d51
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Renamed signals in RAS.
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2023-01-31 10:44:11 -06:00 |
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David Harris
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e96ba254eb
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Removed output delay in synthesis
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2023-01-31 04:37:23 -08:00 |
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Ross Thompson
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0e3c77bed3
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Found small bug in gshare.
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2023-01-31 00:17:49 -06:00 |
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Ross Thompson
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939095615f
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Fixed parameterization in testbench.
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2023-01-31 00:11:01 -06:00 |
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Ross Thompson
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8feac6d242
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Parameterized testbench branch predictor preload.
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2023-01-31 00:08:11 -06:00 |
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Ross Thompson
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238c4d14a9
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More branch predictor cleanup.
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2023-01-30 23:55:52 -06:00 |
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Ross Thompson
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80f50f10d3
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Improved signal names.
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2023-01-30 23:51:04 -06:00 |
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Ross Thompson
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a15889e0aa
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Major cleanup of branch predictor.
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2023-01-30 23:37:34 -06:00 |
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Ross Thompson
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42828e6ec4
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Simplified gshare.
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2023-01-30 19:27:18 -06:00 |
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Ross Thompson
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4cbefd9834
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Minor gshare optimization.
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2023-01-30 18:13:12 -06:00 |
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David Harris
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1121ff0fa7
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Restored top-level modules without import statements
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2023-01-30 12:54:40 -08:00 |
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David Harris
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4a4be04530
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Moved out version of wally using package because synthesis isn't working yet
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2023-01-30 12:48:52 -08:00 |
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David Harris
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a2f66313ea
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-01-30 11:00:51 -08:00 |
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