David Harris
9f24b4c969
Simplified performance counters
2021-12-31 06:40:21 +00:00
Ross Thompson
c79e14fec5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 14:56:24 -06:00
Ross Thompson
b6c9d01f8b
Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.
2021-12-30 14:56:17 -06:00
Ross Thompson
86514a6a23
icache separated from bus fetch fsm. Does not work yet.
2021-12-30 14:23:05 -06:00
David Harris
028a876a4e
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 17:22:22 +00:00
David Harris
d7653dedee
Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion
2021-12-30 17:22:18 +00:00
Ross Thompson
9bcb105aa4
Changed names of Icache signals.
2021-12-30 11:01:11 -06:00
Ross Thompson
077bc35e10
Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu.
2021-12-29 22:24:37 -06:00
David Harris
f441c8e16a
Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot.
2021-12-30 02:38:42 +00:00
David Harris
d8ba97cf71
RV32ic tests running for simple machine with no privileged unit
2021-12-30 02:25:46 +00:00
David Harris
5ac170cb3a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 00:53:44 +00:00
David Harris
98aaa970dd
rv32i regression and linting
2021-12-30 00:53:39 +00:00
Ross Thompson
a16b97cfb4
Added default to busfsm.
2021-12-29 17:53:24 -06:00
Ross Thompson
90ccc94e5e
Moved lsu interlock fpm to separate module.
2021-12-29 17:40:24 -06:00
Ross Thompson
81741925aa
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:35:45 -06:00
Ross Thompson
0782e5c5a6
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:12:29 -06:00
Ross Thompson
1730f644af
Name cleanup in LSU.
2021-12-29 16:34:35 -06:00
Ross Thompson
050523487c
Changed names of lsu address signals.
2021-12-29 15:03:34 -06:00
Ross Thompson
b1116600fe
Added more generates around virtual memory and csrs in the lsu.
2021-12-29 14:48:09 -06:00
Ross Thompson
0c88ddeb5a
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
6052a69ba7
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
1894afd0d8
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
David Harris
e4b4800189
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 00:29:12 +00:00
David Harris
52a38c5856
Added performance counting to sumtest and added imperas32/64periph to testbench.
2021-12-29 00:28:51 +00:00
Ross Thompson
39bd78c295
Changed the bus name between dcache and ebu.
2021-12-28 15:57:36 -06:00
Ross Thompson
13b4201198
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
74d636cb53
First cut at moving the dcache bus interface into the LSU.
...
Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
David Harris
66ad7ddf1c
Added D and F tests to regression
2021-12-27 04:35:34 +00:00
David Harris
e6ed1372a7
Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.
2021-12-26 04:36:53 +00:00
David Harris
48bb534658
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
David Harris
d9e61fad67
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-25 06:37:30 -08:00
David Harris
9b491788b2
Checked in Chapter 2 C and assembly examples
2021-12-25 06:35:36 -08:00
Ross Thompson
7fe70c3cc6
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
...
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
Ross Thompson
f863bdc495
linux-wave.do changes.
2021-12-21 22:37:55 -06:00
Ross Thompson
50b307bc0e
Looks like rdtime was accidentally replaced with rrame from a find and replace.
2021-12-20 21:26:38 -06:00
Ross Thompson
8416cae3fe
Fixed Type 5b interaction between dcache and hptw.
...
This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
d3c3422d12
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
c9291655da
Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
2021-12-19 16:12:31 -06:00
Ross Thompson
a445bedcd2
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
...
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
225cd5a114
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
1126135b80
minro change. comments about needed changes in dcache.
2021-12-19 13:53:02 -06:00
David Harris
0f319b45c1
Do File cleanups
2021-12-17 17:45:26 -08:00
David Harris
865d5ce0b1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
David Harris
ecce1e62ee
changed ideal memory to MEM_DTIM and MEM_ITIM
2021-12-14 13:05:32 -08:00
David Harris
8dcf2c65f2
renamed rv32/64g to rv32/64gc in configuration
2021-12-14 11:22:00 -08:00
David Harris
2039752740
Simplified ALU and source multiplexers pass tests
2021-12-13 07:57:38 -08:00
David Harris
a7e9dee77d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-12 05:49:31 -08:00
Ross Thompson
37079626cd
Fixed numerous errors in the preformance counter updates.
...
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
2021-12-09 11:44:12 -06:00
bbracker
f7b2d3b6df
fix recursive signal logging for graphical sims
2021-12-08 16:07:26 -08:00
David Harris
e14eb9872e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 12:33:59 -08:00
