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old
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bringing Coremark back to life
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2021-11-10 12:43:31 -08:00 |
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slack-notifier
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added slack notifier for long sims
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2021-06-22 08:31:41 -04:00 |
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wave-dos
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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buildrootBugFinder.py
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automatic bug finder script
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2021-11-19 20:25:00 -08:00 |
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fpga-wave.do
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Do File cleanups
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2021-12-17 17:45:26 -08:00 |
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lint-wally
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renamed rv32/64g to rv32/64gc in configuration
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2021-12-14 11:22:00 -08:00 |
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linux-wave.do
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Fixed Type 5b interaction between dcache and hptw.
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2021-12-20 18:33:31 -06:00 |
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make-tests.sh
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add buildroot tv linking to make-tests.sh
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2021-12-07 11:15:59 -08:00 |
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Makefile
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root level makefile added
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2021-11-17 12:17:56 -08:00 |
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regression-wally.py
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renamed rv32/64g to rv32/64gc in configuration
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2021-12-14 11:22:00 -08:00 |
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sim-buildroot
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fix buildroot graphical sim
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2021-10-31 18:33:43 -07:00 |
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sim-buildroot-batch
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change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
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2021-10-25 12:25:32 -07:00 |
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sim-coremark-batch
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Added coremark scripts to regression directory
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2021-12-01 09:08:06 -08:00 |
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sim-fp64
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Update to fpdivsqrt to go on posedge as it should. Also an update to
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2021-10-13 17:14:42 -05:00 |
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sim-fp64-batch
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renamed rv32/64g to rv32/64gc in configuration
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2021-12-14 11:22:00 -08:00 |
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sim-wally
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changed ideal memory to MEM_DTIM and MEM_ITIM
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2021-12-14 13:05:32 -08:00 |
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sim-wally-batch
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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wally-buildroot-batch.do
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change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
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2021-10-25 12:25:32 -07:00 |
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wally-buildroot.do
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fix recursive signal logging for graphical sims
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2021-12-08 16:07:26 -08:00 |
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wally-coremark.do
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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wally-fp64-batch.do
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Update to fpdivsqrt to go on posedge as it should. Also an update to
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2021-10-13 17:14:42 -05:00 |
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wally-fp64.do
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renamed rv32/64g to rv32/64gc in configuration
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2021-12-14 11:22:00 -08:00 |
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wally-pipelined-batch.do
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update scripts for handling src/*/* subdirectories
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2021-10-23 08:54:29 -07:00 |
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wally-pipelined-fpga.do
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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wally-pipelined.do
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Mostly integrated FPGA flow into main branch. Not all tests passing yet.
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2021-12-02 18:00:32 -06:00 |
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wave-all.do
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Do File cleanups
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2021-12-17 17:45:26 -08:00 |
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wave-coremark.do
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Do File cleanups
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2021-12-17 17:45:26 -08:00 |
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wave.do
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Rename of SelPTW to SelHPTW.
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2021-12-19 22:24:07 -06:00 |
