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7fe70c3cc6
cvw/wally-pipelined/regression
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Ross Thompson 7fe70c3cc6 Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages. 
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.

There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment.  This can be cached in the TLB which only costs 1 flip flop
   for each TLB line.
2021-12-23 12:40:22 -06:00
..
old bringing Coremark back to life 2021-11-10 12:43:31 -08:00
slack-notifier added slack notifier for long sims 2021-06-22 08:31:41 -04:00
wave-dos Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
buildrootBugFinder.py automatic bug finder script 2021-11-19 20:25:00 -08:00
fpga-wave.do Do File cleanups 2021-12-17 17:45:26 -08:00
lint-wally renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
linux-wave.do Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages. 2021-12-23 12:40:22 -06:00
make-tests.sh add buildroot tv linking to make-tests.sh 2021-12-07 11:15:59 -08:00
Makefile root level makefile added 2021-11-17 12:17:56 -08:00
regression-wally.py renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
sim-buildroot fix buildroot graphical sim 2021-10-31 18:33:43 -07:00
sim-buildroot-batch change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
sim-coremark-batch Added coremark scripts to regression directory 2021-12-01 09:08:06 -08:00
sim-fp64 Update to fpdivsqrt to go on posedge as it should. Also an update to 2021-10-13 17:14:42 -05:00
sim-fp64-batch renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
sim-wally changed ideal memory to MEM_DTIM and MEM_ITIM 2021-12-14 13:05:32 -08:00
sim-wally-batch Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
wally-buildroot-batch.do change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
wally-buildroot.do fix recursive signal logging for graphical sims 2021-12-08 16:07:26 -08:00
wally-coremark.do Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
wally-fp64-batch.do Update to fpdivsqrt to go on posedge as it should. Also an update to 2021-10-13 17:14:42 -05:00
wally-fp64.do renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
wally-pipelined-batch.do update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
wally-pipelined-fpga.do Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
wally-pipelined.do Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
wave-all.do Do File cleanups 2021-12-17 17:45:26 -08:00
wave-coremark.do Do File cleanups 2021-12-17 17:45:26 -08:00
wave.do Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages. 2021-12-23 12:40:22 -06:00