Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
5,279 Commits 14 Branches 1 Tag 31 MiB
9c5c041122
Commit Graph

5279 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Ross Thompson
9c5c041122 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-04 11:28:26 -06:00
Ross Thompson
9b7a35e848 Updates to imperas test bench. 2023-02-04 11:28:23 -06:00
David Harris
20a03808a1
Merge pull request #62 from davidharrishmc/dev 
../synthDC/Makefile
 2023-02-04 04:29:56 -08:00
David Harris
3f22b62601 Added license headers 2023-02-04 04:29:27 -08:00
David Harris
6b3d056713 ../synthDC/Makefile 2023-02-04 04:19:09 -08:00
David Harris
e2061abda9
Merge pull request #53 from davidharrishmc/dev 
Removed pipelined hierarchy and renamed regression to sim
 2023-02-04 04:15:02 -08:00
David Harris
b13087e706 Fixed merge issues on synthDC PR 2023-02-04 04:13:40 -08:00
David Harris
e0915acad9 Improved illegal NaN-box detection and formatted fsgninj 2023-02-04 03:42:20 -08:00
David Harris
363b7f56a5
Merge pull request #61 from mmasserfrye/main 
USE_SRAM parameter, makefile config cleaning
 2023-02-04 03:28:44 -08:00
Madeleine Masser-Frye
7b0da71297 finishing the job of the last commit 2023-02-04 10:24:01 +00:00
Madeleine Masser-Frye
d9e1323e57 added use sram parameter, cleaned up config writing, added single synth functionality to wallySynth 2023-02-04 09:50:36 +00:00
David Harris
d4a7679926
Merge pull request #60 from ross144/main 
Optimized PCLink logic.
 2023-02-03 16:42:27 -08:00
Ross Thompson
c4a9354c13 Replaced PCLinkX registers with a +2/4 adder in the execution stage. 
David and I estimate this is lower hardware cost.
 2023-02-03 18:19:47 -06:00
Ross Thompson
6dcce8389a Change CurrPtr to Ptr in RAS. 2023-02-03 17:40:20 -06:00
David Harris
ed02d5a077 Removed redundant line from synthesis makefile 2023-02-03 08:36:51 -08:00
David Harris
d7ae05ae8e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-03 08:36:11 -08:00
David Harris
398992db3b Updated division radix test script with paths, but script is out of date for files it manipulates 2023-02-03 08:36:03 -08:00
David Harris
02bdaf858c
Merge pull request #54 from ross144/main 
Fixed issue #50, itlb and dcache flush interlock
 2023-02-03 06:30:30 -08:00
Ross Thompson
370931c1cd Fixed bug #49. 
FFLAGS was updated while the pipeline was stalled.
Also I found serveral performance counters which had similar issues.
 2023-02-03 00:39:26 -06:00
Ross Thompson
a4907b5d29 Lee Moore found another bug using imperas. 
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
 2023-02-02 23:52:21 -06:00
David Harris
a9226e6f73 Removed lab1matrix solutions 2023-02-02 19:40:41 -08:00
David Harris
aae035226f Merged with memories 2023-02-02 14:50:46 -08:00
David Harris
8078cafa27 Renamed regression to sim 2023-02-02 14:48:23 -08:00
David Harris
99d179dd3e Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
David Harris
be618a0c34
Update README.md 2023-02-02 12:59:28 -08:00
James E. Stine
2a87495642
Merge pull request #52 from stineje/main 
Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
 2023-02-02 13:55:17 -06:00
James Stine
bfa69ea2b3 Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22 2023-02-02 13:54:25 -06:00
David Harris
4c50166e56
Merge pull request #51 from stineje/main 
Modify generic/mem for rv32gc ram2
 2023-02-02 11:41:32 -08:00
James Stine
b66177fd87 Modify generic/mem for rv32gc ram2 2023-02-02 13:28:18 -06:00
David Harris
551594e021 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-02 10:28:40 -08:00
David Harris
bc0ca38b2f
Merge pull request #48 from ross144/main 
Fixed bug #47, ecall and ebreak don't commit
 2023-02-02 06:58:07 -08:00
Ross Thompson
091aadff0e Merge branch 'main' of github.com:ross144/cvw 2023-02-02 08:52:48 -06:00
Ross Thompson
230888db8b Fixed bug #47 discovered by Lee Moore. 
ECALL and EBREAK do not commit their results.
 2023-02-02 08:52:06 -06:00
Ross Thompson
d62a72a76f Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-02-02 08:48:19 -06:00
Ross Thompson
a8afdf1741 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-01 19:24:10 -06:00
David Harris
93f57402df Removed O2 from fir Makefile to be consistent with lab. 2023-02-01 15:43:52 -08:00
David Harris
c214a9e8fc
Merge pull request #45 from stineje/main 
Update ram2 and other memories and associated wrappers
 2023-02-01 15:06:30 -08:00
James Stine
6ce80b6b8a Update ram2 and other memories and associated wrappers 2023-02-01 17:03:48 -06:00
Ross Thompson
0035579553 Minor branch predictor bug fix. 2023-02-01 10:59:38 -06:00
Ross Thompson
2a5b6408f2 Removed unused signal. 2023-02-01 10:27:58 -06:00
David Harris
129380db0b Fixed typo in DC setup for memories 2023-02-01 05:49:30 -08:00
David Harris
c9b56f9acc Only add memory libraries when targeting 28nm 2023-02-01 05:06:56 -08:00
David Harris
73b29e1f71
Merge pull request #36 from davidharrishmc/dev 
RV32imc configuration
 2023-02-01 04:44:36 -08:00
David Harris
0280942563 Fixed merge conflict to get synthesis working again 2023-02-01 04:43:57 -08:00
David Harris
838bb21077
Merge pull request #43 from mmasserfrye/main 
ram size, bpred size, memories *SYNTH NOT FUNCTIONAL*
 2023-02-01 04:13:37 -08:00
Ross Thompson
c3e3afe398 Minor change to btb. 2023-02-01 00:24:54 -06:00
Madeleine Masser-Frye
ad6d7eb5e2 added memories (not tested) 2023-02-01 06:08:27 +00:00
Ross Thompson
a9624b1413 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-01 00:01:14 -06:00
Madeleine Masser-Frye
c78adbb8e7 increased bpred size to (2^) 5 2023-02-01 05:51:31 +00:00
Madeleine Masser-Frye
02a1432c46 updated synth makefile to change all relevant 
ram ranges to 1FF
 2023-02-01 05:40:35 +00:00