slmnemo
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98c07ce2c0
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Added more comments
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2022-06-13 12:26:08 -07:00 |
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slmnemo
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3d715a098c
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Added comment about name of LSUBusInit/Lock signal
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2022-06-13 10:56:02 -07:00 |
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slmnemo
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cadd62e49f
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Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
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2022-06-10 20:43:56 -07:00 |
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slmnemo
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beb4317e68
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Added comments to signals added so the bus is easier to analyze
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2022-06-10 20:30:04 -07:00 |
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slmnemo
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b7357efc6b
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Fixed failed regression state by only enabling counting when doing cached operations
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2022-06-10 20:00:09 -07:00 |
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slmnemo
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63ed390c90
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Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
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2022-06-10 19:10:01 -07:00 |
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slmnemo
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dc11066ff2
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Passed Regression: Seems to work perfectly fine
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2022-06-09 18:21:13 -07:00 |
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slmnemo
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ec7cdee0f3
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Merge branch 'main' into cacheburstmode
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2022-06-09 17:51:03 -07:00 |
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slmnemo
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5a6eae214a
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?
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2022-06-09 17:50:47 -07:00 |
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slmnemo
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3e8d3bae88
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Changes made on 9th Jun
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2022-06-09 17:33:51 -07:00 |
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slmnemo
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4ff105f18c
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Fixed lint error
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2022-06-09 17:22:04 -07:00 |
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David Harris
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c836f37a08
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New RAM for further testing
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2022-06-09 23:50:43 +00:00 |
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stineje
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470c0552f8
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Update integer division for r4 and qslc_r4a2.c
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2022-06-09 16:45:13 -05:00 |
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David Harris
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dd4fa7c682
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qslc_r4a2 generator
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2022-06-09 17:26:47 +00:00 |
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slmnemo
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0d04751c77
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Fixed error when doing uncached accesses where HTRANS was always 2
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2022-06-08 18:58:07 -07:00 |
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slmnemo
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81d373c7ab
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Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
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2022-06-08 17:34:02 -07:00 |
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Madeleine Masser-Frye
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0e64494e46
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-09 00:08:15 +00:00 |
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Madeleine Masser-Frye
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a58a756076
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added one bit muxes for data critical synths
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2022-06-09 00:06:12 +00:00 |
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slmnemo
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11924bdd9b
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Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending
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2022-06-08 15:59:15 -07:00 |
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slmnemo
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e17ee3073e
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Fixed ifu displaying LSU bus state in wave.do
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2022-06-08 15:30:32 -07:00 |
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slmnemo
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315c2f0669
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Working version: Fixed error where Word count would always increment even without AHB to bus ACK
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2022-06-08 15:29:32 -07:00 |
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slmnemo
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054cf5f7b0
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Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
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2022-06-08 15:03:15 -07:00 |
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DTowersM
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6402b2dec4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-08 16:28:18 +00:00 |
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DTowersM
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6944996329
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added #1 delays to Stalls and Flushes in hazard unit
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2022-06-08 16:28:09 +00:00 |
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slmnemo
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284e0395a0
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Merge branch 'main' into cacheburstmode
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2022-06-08 02:21:33 +00:00 |
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slmnemo
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2d76953d42
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Added lock signal to ensure AHB speaks with the right bus
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2022-06-08 02:19:21 +00:00 |
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David Harris
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5240bd1c90
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Modified RAM for single-cycle latency
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2022-06-08 02:06:00 +00:00 |
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David Harris
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3c8eafc8ee
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Cleaned bram interface
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2022-06-08 01:39:44 +00:00 |
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David Harris
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9e5ab4d378
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Added ahbapbbridge and cleaning RAM
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2022-06-08 01:31:34 +00:00 |
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DTowersM
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a190342b8a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 23:58:58 +00:00 |
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DTowersM
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02a424d65b
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modified testbench.sv- now works with coremark
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2022-06-07 23:58:50 +00:00 |
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DTowersM
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e324db71b4
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cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
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2022-06-07 23:27:54 +00:00 |
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slmnemo
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6d36150c3d
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Fixed off-by-one error in busdp capture
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2022-06-07 19:36:39 +00:00 |
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slmnemo
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73e0c1c07f
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Reworked bus to handle burst interfacing
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2022-06-07 11:22:53 +00:00 |
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DTowersM
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df330961b8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 06:03:19 +00:00 |
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DTowersM
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590cf243bb
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added support for 64 bit rv tests
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2022-06-07 06:02:23 +00:00 |
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Katherine Parry
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cfcaddf8aa
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-06 16:06:54 +00:00 |
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Katherine Parry
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8fa0fc4229
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fma synth warnings and errors removed
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2022-06-06 16:06:04 +00:00 |
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slmnemo
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7f70655113
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-03 18:56:29 -07:00 |
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slmnemo
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3fe78c9084
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Fixed recurrent issue with testbench where it would never stop
|
2022-06-03 18:56:24 -07:00 |
|
cturek
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afdfe770fc
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Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench.
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2022-06-04 00:14:10 +00:00 |
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DTowersM
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caaf56cbf7
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testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh
|
2022-06-03 22:07:14 +00:00 |
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Madeleine Masser-Frye
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56a053fc3d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-03 21:08:49 +00:00 |
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Madeleine Masser-Frye
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31e9d0a41a
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added muxes and inv, fixed priority encoder
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2022-06-03 21:03:13 +00:00 |
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Katherine Parry
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fd980fe9d6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-03 15:34:27 +00:00 |
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Katherine Parry
|
6b39b8c702
|
fixed compilation errors
|
2022-06-03 15:34:17 +00:00 |
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slmnemo
|
9d1dfbdb50
|
Changed NO_SPOOFING from 0 to 1 in buildroot-no-trace to better facilitate wally booting linux without following QEMU's trace
|
2022-06-03 04:55:14 -07:00 |
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Katherine Parry
|
8420b1e87c
|
removed some debuging code accedentally pushed
|
2022-06-02 22:45:19 +00:00 |
|
Katherine Parry
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6a4502e987
|
added rv64fpquad
|
2022-06-02 22:10:00 +00:00 |
|
Katherine Parry
|
cd8b2a2b98
|
added config rv64fpquad
|
2022-06-02 22:09:11 +00:00 |
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