Ross Thompson
8e4467654a
Working without dcache.
2021-12-30 16:01:31 -06:00
Ross Thompson
6c45da022b
Progress on non dcache mode working.
2021-12-30 15:51:07 -06:00
Ross Thompson
9136b1fd73
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 15:26:41 -06:00
Ross Thompson
6b59c03d1b
No dcache now supported. Does not pass regression tests however.
2021-12-30 15:26:32 -06:00
David Harris
347896064d
Removed unnecessary generate inside hptw
2021-12-30 21:21:00 +00:00
Ross Thompson
c79e14fec5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 14:56:24 -06:00
Ross Thompson
b6c9d01f8b
Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.
2021-12-30 14:56:17 -06:00
David Harris
2327f4b6bf
Added names to generate blocks
2021-12-30 20:55:48 +00:00
Ross Thompson
077bc35e10
Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu.
2021-12-29 22:24:37 -06:00
Ross Thompson
7765178a04
Rename of dcache interface signals.
2021-12-29 21:26:15 -06:00
David Harris
5ac170cb3a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 00:53:44 +00:00
David Harris
98aaa970dd
rv32i regression and linting
2021-12-30 00:53:39 +00:00
Ross Thompson
a16b97cfb4
Added default to busfsm.
2021-12-29 17:53:24 -06:00
Ross Thompson
90ccc94e5e
Moved lsu interlock fpm to separate module.
2021-12-29 17:40:24 -06:00
Ross Thompson
81741925aa
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:35:45 -06:00
Ross Thompson
0782e5c5a6
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:12:29 -06:00
Ross Thompson
1730f644af
Name cleanup in LSU.
2021-12-29 16:34:35 -06:00
Ross Thompson
050523487c
Changed names of lsu address signals.
2021-12-29 15:03:34 -06:00
Ross Thompson
b1116600fe
Added more generates around virtual memory and csrs in the lsu.
2021-12-29 14:48:09 -06:00
Ross Thompson
bc437cf7e0
Cleaned up some names in dcache and lsu.
2021-12-29 11:21:44 -06:00
Ross Thompson
fe22d4544f
Converted mux4 to mux3 in dcache.
2021-12-29 10:58:02 -06:00
Ross Thompson
0c88ddeb5a
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
6052a69ba7
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
1894afd0d8
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
Ross Thompson
76d1dc1721
LSU Bus FSM beautification.
2021-12-28 16:53:53 -06:00
Ross Thompson
e29803be30
Removed CommittedM as it is redundant with LSUStall.
2021-12-28 16:14:10 -06:00
Ross Thompson
39bd78c295
Changed the bus name between dcache and ebu.
2021-12-28 15:57:36 -06:00
Ross Thompson
d62cd1f701
Reverted changes to subwordread while keeping the new names of the i/o.
2021-12-28 15:57:21 -06:00
Ross Thompson
9c190b019b
Name changes for states in LSU.
2021-12-28 15:03:24 -06:00
Ross Thompson
13b4201198
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
f09b10a393
Moved generate for lrsc to lsu.
2021-12-28 14:17:18 -06:00
Ross Thompson
73af458eb5
More cleanup of dcache.
2021-12-28 14:12:18 -06:00
Ross Thompson
0e86e5d9f1
Additional cleanup of the LSU.
2021-12-28 13:59:07 -06:00
Ross Thompson
1e76c24f26
Major cleanup of the LSU.
2021-12-28 13:10:45 -06:00
Ross Thompson
79b17c5b55
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
34c11ca8d5
Minor dcache cleanup.
2021-12-28 11:29:16 -06:00
Ross Thompson
243728d089
Moved all bus logic outside the dcache. Still needs cleanup.
2021-12-28 11:18:47 -06:00
Ross Thompson
74d636cb53
First cut at moving the dcache bus interface into the LSU.
...
Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
Ross Thompson
d366a1f50f
Moved dcache fetch logic outside the dcache except for the fsm.
2021-12-27 16:45:49 -06:00
Ross Thompson
e3ddcbb11e
Partial commit.
...
Moved AMO, SWW, and SWR outside the dcache.
Step 1 of separate the fetching logic from the caches.
2021-12-27 15:56:18 -06:00
Ross Thompson
6a8e917e06
It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.
2021-12-21 15:59:56 -06:00
Ross Thompson
8416cae3fe
Fixed Type 5b interaction between dcache and hptw.
...
This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
b6d75d453a
Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.
2021-12-20 10:03:56 -06:00
Ross Thompson
beb1988539
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
df8bd78679
More signal name cleanup in LSU.
2021-12-19 22:47:48 -06:00
Ross Thompson
3eb5f33705
Remove verbosity from lsu state machine.
2021-12-19 22:41:34 -06:00
Ross Thompson
d3c3422d12
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
8feb36b926
Signal renames.
2021-12-19 22:21:03 -06:00
Ross Thompson
dc82d44f9e
Hardware reductions in the lsu.
2021-12-19 22:00:28 -06:00
Ross Thompson
138da1fefa
Removed lsuArb and placed remaining logic in lsu.sv.
...
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
2021-12-19 21:34:40 -06:00
