David Harris
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aa31b45d88
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Fixed RV32 tests after PMP fix
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2023-03-28 08:35:23 -07:00 |
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David Harris
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39d3bf8e8a
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Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
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2023-03-28 06:58:17 -07:00 |
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Kip Macsai-Goren
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b856698ce2
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Revert "added premilinary boundary ccrossing cases"
This reverts commit 3ce82f93c0.
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2023-03-24 11:27:41 -07:00 |
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Kip Macsai-Goren
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e949d3dc4b
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ported fixes to 32 bit tests
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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f0027aef23
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replaced inerrupt tests with allowed versions
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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3c6b856068
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Added cause_s_soft_from_m_interrupt
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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3ce82f93c0
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added premilinary boundary ccrossing cases
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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5c3f5fe8c6
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added in the CSR name for stimecmp(h)
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2023-03-04 15:53:03 -08:00 |
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Kip Macsai-Goren
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4fa78a02b7
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removed changes to counteren from stimecmp tests
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2023-03-04 15:46:57 -08:00 |
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Kip Macsai-Goren
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da9627708e
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Added correct causing and handling of S time interrupts to test suite.
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2023-03-04 15:04:17 -08:00 |
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David Harris
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fe0a893182
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Renamed section 12.3 to 8.3 in MMU test definitions
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2023-02-19 05:46:46 -08:00 |
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David Harris
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8b34f5ac98
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-01-28 18:18:53 -08:00 |
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Kip Macsai-Goren
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95b26c49b9
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Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts.
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2023-01-28 17:29:35 -08:00 |
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David Harris
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71d1c8fc68
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Removed unused WALLY test references
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2023-01-27 07:25:04 -08:00 |
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David Harris
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ae7d23380a
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Removed unused reference files
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2023-01-27 07:21:55 -08:00 |
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Kip Macsai-Goren
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ffae1c5ee6
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added fs=00 to status fp enabled test
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2022-12-22 15:15:53 -08:00 |
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Kip Macsai-Goren
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a768d70093
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Kip Macsai-Goren
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7aadf50f26
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updated trap handler alignemnts to 64 bytes in priv tests
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2022-12-22 14:23:04 -08:00 |
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David Harris
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c7f3aae084
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Only delegated bits of SIP are readable
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2022-12-21 12:32:49 -08:00 |
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Ross Thompson
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c3b43b2fac
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Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
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2022-12-21 13:16:09 -06:00 |
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Ross Thompson
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0b4186f1e8
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Vectored interrupts now require 64 byte alignment.
Eliminates adder.
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2022-12-21 12:05:49 -06:00 |
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Kip Macsai-Goren
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2dfa426e10
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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1d268fded4
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added corrrect scr read out of uart to periph test
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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7411d50a78
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added all 32 bit tests to 64 bit periph tests except gpio
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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badc684f07
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added copies of 64 bit tests to 32 bit periph and priv tests
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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282d06b45f
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added -01 to all WALLY tests
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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af00eadec2
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added tests for invalid address being written to satp. Not passing regression
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2022-11-27 13:22:35 -08:00 |
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Kip Macsai-Goren
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6fdd603ba1
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added potential fix to overrun error and fifo interrupt error. test passes
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2022-11-06 22:01:02 -08:00 |
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Kip Macsai-Goren
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b42fc7ec6d
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fixed fifo timout handling. error now in data ready interrupt
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2022-11-05 13:34:24 -07:00 |
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Kip Macsai-Goren
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23268d22e5
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fixed broken instructions so make works.
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2022-11-03 23:06:20 +00:00 |
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Ross Thompson
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f81d1e15b6
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More outline for uart timeout interrupt.
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2022-10-28 13:53:56 -05:00 |
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Ross Thompson
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372b9890ef
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Untested change to uart test for outline of how to handle rx fifo timeout.
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2022-10-28 13:31:16 -05:00 |
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Kip Macsai-Goren
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d4dd2dcc08
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Added test for UART FIFO timeout. Does not pass regression
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2022-10-25 05:35:56 +00:00 |
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Kip Macsai-Goren
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d5cd67cf09
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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Kip Macsai-Goren
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0d2fcaeab1
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added xlen and endianness test edits. xlen passes but endinanness still won't make
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2022-09-26 05:03:19 +00:00 |
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Kip Macsai-Goren
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3f4c825a1a
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added mstatus uxl, sxl bit tests (not tested in regression yet)
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2022-09-18 00:11:29 +00:00 |
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Kip Macsai-Goren
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dda3b2d383
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ported endianness tests to 32 bits (not tested in regression yet)
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2022-09-18 00:10:29 +00:00 |
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Kip Macsai-Goren
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99596fac84
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Fixed typos in existing endianness test
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2022-09-18 00:09:52 +00:00 |
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Kip Macsai-Goren
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657e19df08
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added full coverage of subword loads and stores to endianness test
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2022-09-17 23:14:38 +00:00 |
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Kip Macsai-Goren
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a4fc5d3476
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Created initial endianness tests
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2022-09-16 01:06:26 +00:00 |
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David Harris
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8b8f045491
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Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
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David Harris
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62252c2167
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Debugging plic-s test
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2022-08-03 13:21:09 +00:00 |
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David Harris
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6ee8036ae7
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plic-s debug
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2022-08-03 12:33:09 +00:00 |
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David Harris
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e3ea86f984
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Started plic-s tests
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2022-08-03 03:48:08 +00:00 |
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David Harris
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d2de84a456
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Added parity and stop bit tests to UART
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2022-07-28 04:35:51 +00:00 |
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David Harris
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763a6d7340
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Fixed UART reference output
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2022-07-27 22:16:38 +00:00 |
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David Harris
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f61f0645fe
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Finished UART test
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2022-07-27 04:06:59 +00:00 |
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slmnemo
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a32698811d
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Updated reference file for UART test
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2022-07-26 09:39:31 -07:00 |
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slmnemo
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528dfd9170
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Committing changes made to UART test
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2022-07-26 09:14:40 -07:00 |
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slmnemo
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5b71ceac5c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 17:13:38 -07:00 |
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