Thomas Fleming
6188f10732
Move InstrPageFault to fetch stage
2021-04-13 13:39:22 -04:00
Thomas Fleming
dc8a165806
Add lru algorithm to TLB
2021-04-13 13:37:24 -04:00
Teo Ene
03bb37a849
Fixed synthesis log error caused by typo in synthesis script
2021-04-13 12:12:36 -05:00
Teo Ene
a426b3f199
Changed default target synth frequency
2021-04-13 11:48:30 -05:00
Teo Ene
1018a10625
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Jarred Allen
4ae1df1290
Merge branch 'main' into cache
2021-04-13 01:10:03 -04:00
Jarred Allen
fc8b8ad7aa
A few more cache fixes
2021-04-13 01:07:40 -04:00
Ross Thompson
35f8b4f74f
Fixed minor bug in muldiv which corrects the lint error.
2021-04-09 10:56:31 -05:00
ushakya22
99f2d24e05
Latest IE tests with timer interupts
2021-04-08 17:53:39 -04:00
Jarred Allen
d99b8f772e
Merge from branch 'main'
2021-04-08 17:19:34 -04:00
Ross Thompson
e73e16e57a
Created special test for driving the instruction spill error.
...
The extact problem occurs when a 4 byte instruction startles two cache blocks (or without a cache two ahbi words) and the code jumps to a cache block other than the next cache block. Consider the following sample of code.
0000000000000080 <test_spill>:
80: 42a9 li t0,10
82: 0001 nop
84: 0001 nop
86: 0001 nop
88: 02bd addi t0,t0,15
8a: 00628e33 add t3,t0,t1
8e: 01ce8963 beq t4,t3,a0 <match>
0000000000000092 <failure>:
92: 557d li a0,-1
94: 8082 ret
96: 00000013 nop
9a: 00000013 nop
9e: 0001 nop
00000000000000a0 <match>:
a0: 1ffd addi t6,t6,-1
a2: fc0f9fe3 bnez t6,80 <test_spill>
a6: 4501 li a0,0
a8: 8082 ret
Instructions 0x88, 0x8a and 0x8e are read incorrectly. However once the branch predictor begins to correctly predict the beq at 0x8e the instrution at 0xa0 is loaded incorrectly as the 2 upper bytes of 0x8e and the two bytes of 0x92. This amalgamation causes c.addi at 0xa0 to do something else and the loop never terminates.
The button of wavefile wave.do shows the exact problem in the 'icache'.
2021-04-08 15:05:08 -05:00
bbracker
1ee8feffe5
integrated peripheral testing into existing workflow
2021-04-08 15:31:39 -04:00
bbracker
005f838b8d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 14:28:25 -04:00
bbracker
755e2e5771
merge testbench
2021-04-08 14:28:01 -04:00
Katherine Parry
b7ebfd66ed
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 18:06:51 +00:00
David Harris
8549e457c1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 14:04:09 -04:00
David Harris
6b2868a8c7
restored testbench-imperas.sv
2021-04-08 14:04:01 -04:00
Katherine Parry
2ee015d53e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 18:03:57 +00:00
Katherine Parry
f4cb92ae71
fixed FPU lint warnings
2021-04-08 18:03:21 +00:00
Katherine Parry
27cb94e7af
fixed FPU lint warnings
2021-04-08 17:55:25 +00:00
ushakya22
72a64edfb8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 13:55:23 -04:00
ushakya22
b0f6898ece
Updates to WALLY-IE tests
2021-04-08 13:54:42 -04:00
David Harris
ac8a111d61
merge conflict resolution
2021-04-08 13:53:56 -04:00
David Harris
6a6ccca3c8
fixed sim-wally-32ic
2021-04-08 13:40:16 -04:00
Noah Boorstin
14d2ad1e2d
try to remove git-lfs stuff
2021-04-08 13:23:11 -04:00
Domenico Ottolia
3067e94b4b
Update privileged testgen & helper script
2021-04-08 05:14:07 -04:00
Domenico Ottolia
65abe13f4f
Cause an Illegal Instruction Exception when attempting to write readonly CSRs
2021-04-08 05:12:54 -04:00
Thomas Fleming
fc39535e4e
Refactor TLB into multiple files
2021-04-08 03:24:10 -04:00
Thomas Fleming
c54aecde73
Provide attribution link for priority encoder
2021-04-08 03:05:06 -04:00
Thomas Fleming
303c2c4839
Implement support for superpages
2021-04-08 02:44:59 -04:00
Ross Thompson
4322694f7a
Switch to use RV64IC for the benchmarks.
...
Still not working correctly with the icache.
instr
addr correct got
2021-04-07 19:12:43 -05:00
ushakya22
83d9aa3a50
MIE privilege tests with working timer interupt
2021-04-07 04:09:09 -04:00
ushakya22
fd5a1f3874
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-07 04:06:54 -04:00
Domenico Ottolia
60cf38192b
Add privileged tests to testbench
2021-04-07 02:22:08 -04:00
Domenico Ottolia
465d3986b0
Add passing mtval and mepc tests
2021-04-07 02:21:05 -04:00
Ross Thompson
c91436d3b7
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Ross Thompson
98a04abe6c
Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
2021-04-06 21:20:55 -05:00
Ross Thompson
bff2d61a1f
Steps to getting branch predictor benchmarks running.
2021-04-06 21:20:51 -05:00
Jarred Allen
bd8f1eea3c
Fix another bug in icache
2021-04-06 17:47:00 -04:00
Jarred Allen
3afc358974
Fix another bug in icache
2021-04-06 12:48:42 -04:00
ushakya22
4ac4cf2aaa
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-06 12:29:23 -04:00
Noah Boorstin
284d583877
add busybear boot files with git-lfs
2021-04-05 19:38:43 -04:00
Noah Boorstin
0e3f013212
busybear: reenable 'ruthless' CSR checking
2021-04-05 12:53:30 -04:00
bbracker
38017e6aae
declare memread signal
2021-04-05 08:13:01 -04:00
bbracker
a4c3afb847
PLIC claim reg side effects now check for memread signal
2021-04-05 08:03:14 -04:00
bbracker
4a5aa5b202
plic subword access compliance
2021-04-04 23:10:33 -04:00
Katherine Parry
e6a7353847
Added missing files in FPU
2021-04-04 18:09:13 +00:00
bbracker
31c6b2d01f
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Thomas Fleming
6b43381c38
Comment out fpu from hart until module exists
2021-04-03 22:34:11 -04:00
Thomas Fleming
dbd5a4320e
Merge branch 'mmu' into main
...
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
2021-04-03 22:12:52 -04:00
