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8cb4a7a69a
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52 Commits

Author SHA1 Message Date
Cedar Turek
8cb4a7a69a Commented fdivsqrt module 2022-12-30 10:52:25 -08:00
Cedar Turek
3115df9380 Begin commenting divsqrt 2022-12-30 10:43:02 -08:00
David Harris
776f4714af Clean up names and comments in divsqrt 2022-12-29 08:02:44 -08:00
David Harris
d59878a886 Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc 2022-12-27 21:53:00 -08:00
David Harris
dfc0b5d1ad Removed MDUE from unnecessary places in fdivsqrt 2022-12-27 10:42:40 -08:00
Cedar Turek
f48b7d7ef9 fpu idiv working on all configs with 1 copy of radix 2! 2022-12-26 23:18:28 -08:00
Cedar Turek
bebaf08bed took out otfc swap. updated postprocessing quotient/remainder logic for int div. 2022-12-26 21:03:56 -08:00
David Harris
2de66e9eef Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
cturek
cc6f219bdd Added A Sign register. Fixed postprocessing logic for postinc and rem calculation. 2022-12-24 06:46:52 +00:00
David Harris
9e21358d75 Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
David Harris
0a7ed944a5 Revert to 98b824 2022-12-22 23:58:14 -08:00
David Harris
56312cd0a6 Clean up unused FPU signals 2022-12-22 23:53:09 -08:00
David Harris
4d509f94ec FDIV merge 2022-12-22 23:03:03 -08:00
David Harris
2d72bed1f4 Removed unused signals in FPU and CSR 2022-12-22 22:59:05 -08:00
cturek
ccbad67497 Added negative-result int diviison support in U and UM registers. 13 tests pass! 2022-12-22 16:25:37 +00:00
cturek
80ca75e216 Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc. 2022-12-22 05:44:55 +00:00
cturek
c3fdc0ab23 Renamed signals to E and M stages, forwarded preprocessed n to fsm 2022-12-22 00:43:27 +00:00
Alessandro Maiuolo
5a82898649 Added NumZeroE, AZeroM, and BZeroM 2022-12-18 20:02:40 -08:00
cturek
06c58f310d Added mux for integer special case, renamed signals to match pipelined stage 2022-12-16 18:43:49 +00:00
cturek
d7571bb9b1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-16 03:41:39 +00:00
David Harris
4365c99b52 Refactored stalls and flushes, including FDIV flush with FlushE 2022-12-15 10:56:18 -08:00
David Harris
5f637ef4a7 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
cturek
8829e627eb Fixed BZero and initU/initUM muxes 2022-12-14 16:44:46 +00:00
cturek
f57211bb49 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs 2022-12-10 21:56:35 +00:00
Ross Thompson
de99663b97 Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 
This reverts commit 70b89e5214.
 2022-12-04 00:01:58 +00:00
cturek
70b89e5214 Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider. 2022-12-02 21:44:29 +00:00
cturek
1f32603c30 Added flops to preproc 2022-12-02 20:31:08 +00:00
David Harris
d64cd715f9 Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
David Harris
9c1b7e53e4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
cturek
7140642c93 Almost done with Int division 2022-11-22 22:22:59 +00:00
David Harris
ddba68605e Renamed DivBusy to FDivBusyE in FPU 2022-11-16 10:13:27 -08:00
David Harris
e008d663f4 Moved DivStartE to fdivsqrtfsm 2022-11-16 10:00:07 -08:00
cturek
74f58b5d89 Added Quotient/Remainder calcs to normal termination 2022-11-13 23:44:34 +00:00
cturek
b3bfdbad18 Added flops for n and m, added B=0 signal 2022-11-13 23:02:43 +00:00
cturek
9c70ab917c Added A<B signal to fdivsqrt, started postprocessing merge 2022-11-13 22:40:26 +00:00
cturek
ff410cd849 Added integer step counter to fsm 2022-11-11 00:23:25 +00:00
cturek
1e927df1a0 Added conditional OTFC swap for simplified int postprocessing 2022-11-06 23:09:09 +00:00
cturek
333da5c945 Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench. 2022-11-06 22:08:18 +00:00
cturek
b893d9249d Added new macros for int div preprocessing, added p, n, and rightshiftx logic 2022-11-06 21:53:48 +00:00
cturek
39bf6a456e renamed remOp to RemOp 2022-11-03 22:37:25 +00:00
cturek
890b26466f Added rem/div operation to postprocessor 2022-11-02 17:49:40 +00:00
cturek
51fc4de0e1 small signal cleanup 2022-10-26 18:42:49 +00:00
cturek
94daa961b3 Started Integer Preprocessing 2022-10-25 17:48:43 +00:00
amaiuolo
a0712d1456 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-10-13 22:36:57 +00:00
amaiuolo
000117fcd4 added amaiuolo@hmc.edu 2022-10-13 22:36:52 +00:00
David Harris
55e4911cf0 fdivsqrt code cleanup 2022-10-09 03:37:27 -07:00
David Harris
fc4146f409 Adding start signals for integer divider to fdivsqrt 2022-09-29 16:30:25 -07:00
cturek
c72e2e5d49 Added integer inputs and flags to divsqrt 2022-09-29 23:08:27 +00:00
David Harris
b21e36a788 Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc 2022-09-21 04:55:43 -07:00
David Harris
437fd52bf6 Gated sticky bit in fdiv with SpecialCase 2022-09-20 20:05:00 -07:00