ethan-falicov
9edc4b6bfe
Fixed merge conflict stuff
2021-02-10 10:03:30 -05:00
ethan-falicov
7e8a58de1a
More merge conflicts yay
2021-02-10 09:54:30 -05:00
ethan-falicov
f778f464b7
Merge conflict fixing
2021-02-10 09:45:47 -05:00
ethan-falicov
06541260e0
Adding I Type test cases from Lab 1
2021-02-10 09:39:43 -05:00
Jarred Allen
403a0d033c
Fix compile error in imperas testbench
2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
81a1eb9a74
merge conflict?
2021-02-07 02:34:49 -05:00
Jarred Allen
48ade25577
Actually run the WALLY-LOAD tests
2021-02-06 14:56:40 -05:00
Jarred Allen
edd758453e
Add test vector set for load instructions
2021-02-06 13:05:59 -05:00
bbracker
691d651fde
JAL testing
2021-02-05 08:08:42 -05:00
Thomas Fleming
8588a1ed6b
Complete STORE tests
2021-02-04 15:38:22 -05:00
Brett Mathis
79cb7ed571
Parallel FSR's and F CTRL logic
2021-02-04 02:25:55 -06:00
Jarred Allen
ea791cb057
Change busybear test to use work-busybear library
2021-02-03 11:12:47 -05:00
Jarred Allen
743695400d
Start on a test set for loads
2021-02-03 00:37:43 -05:00
David Harris
91f6858de7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 19:44:43 -05:00
David Harris
a44c2abb12
Minor tweaks
2021-02-02 19:44:37 -05:00
Jarred Allen
10f023b44d
Refactor regression test
2021-02-02 17:22:29 -05:00
Noah Boorstin
b370be4a8a
Add busybear testbench to nightly regression checking
...
If you don't like how I did this please feel free to undo it
2021-02-02 22:05:35 +00:00
Noah Boorstin
00d9e13d68
same thing but do that right this time
2021-02-02 21:47:15 +00:00
Noah Boorstin
56ff32f857
change undefined syntax in extend.sv
...
don't need verilator execption anymore
2021-02-02 21:39:20 +00:00
David Harris
d56d7a75a6
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
aee44bb343
Changed DTIM latency to 2 cycles
2021-02-02 14:22:12 -05:00
David Harris
4fbb5f0f1b
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
David Harris
e661b32821
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 13:42:35 -05:00
David Harris
c23afbda3a
Moved LoadStall generation to IEU
2021-02-02 13:42:23 -05:00
David Harris
aad1d3d7dd
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
Jarred Allen
5090537f3c
Fix intermittent errors caused by weird library stuff
2021-02-02 11:20:09 -05:00
Noah Boorstin
8d53e36bbc
Busybear: start checking CSRs
...
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)
and 3 of the CSRs referenced are skipped because of weird locations for them
oh and this doesn't check their initial state, just their changing. This could be a problem
2021-02-02 06:06:03 +00:00
David Harris
9d7e242596
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
Jarred Allen
2b75e38239
Fix issues in parallel regression testing
2021-02-01 23:29:03 -05:00
Noah Boorstin
c634b2f81e
busybear: start adding CSR checking
...
@kaveh is there a less verbose way to do this?
2021-02-01 22:08:51 -05:00
Brett Mathis
94de3e9fb2
OSU FPU IP initial commit
2021-02-01 19:33:43 -06:00
Noah Boorstin
ff88214730
busybear: change register file checking to only store register changed
...
this should make parsedRegs.txt much smaller
2021-02-02 01:27:43 +00:00
Noah Boorstin
416b3fc96c
Add PCW checking
...
for now, doesn't check InstrW because it fails on compressed instructions
2021-02-01 23:57:33 +00:00
David Harris
056b147b13
Renamed DCU to DMEM
2021-02-01 18:52:22 -05:00
Jarred Allen
84801213d6
Parallelize regression-wally.p
2021-02-01 15:40:27 -05:00
Noah Boorstin
a432d607ce
busybear: print warning when NOPing out instructions
2021-02-01 19:44:56 +00:00
Noah Boorstin
b7f63c1dc7
busybear: NOP out floating point instructions for now
...
Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
2021-01-30 19:52:47 +00:00
Noah Boorstin
4358f086be
update busybear testbench to conform to new structure
...
aaaaaaaaaaaaaaaaaahhhh so many changes
also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
2021-01-30 19:19:00 +00:00
David Harris
396cea1ea7
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
David Harris
fc1fb94217
Working on reading instruction from TIM
2021-01-30 01:57:51 -05:00
David Harris
61fd7c4499
Adding stalls for memory delays
2021-01-30 01:43:49 -05:00
David Harris
9c81278f28
Added HCLK and HRESETn
2021-01-30 00:56:12 -05:00
David Harris
a357f2a0e7
Connected AHB bus to Uncore
2021-01-29 23:43:48 -05:00
David Harris
73a584b223
Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team
2021-01-29 18:06:36 -05:00
David Harris
e700e404c9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 17:29:01 -05:00
David Harris
9a51bb27c3
Implemented adrdec for uncore
2021-01-29 17:28:53 -05:00
Teo Ene
9eafdbe349
- Removed latch on CSRCReadValM in csrc.sv
...
- Changed top level to wallypipelinedhart
2021-01-29 15:56:51 -06:00
David Harris
8d4f5277d2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 15:38:01 -05:00
David Harris
dc2443c55b
Moving data memory to uncore
2021-01-29 15:37:51 -05:00
Teo Ene
3d02d6f09f
Added AHBW to rv32ic config file as well
2021-01-29 12:29:08 -06:00
