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Author SHA1 Message Date
David Harris
9b20bf341e Moved lsuvirtmem muxes into hptw 2022-11-07 11:13:34 -08:00
Ross Thompson
fd1ef82310 Fixed bug with fpga makefile. 2022-11-07 09:20:05 -06:00
Ross Thompson
922513c22f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-07 09:10:51 -06:00
Kip Macsai-Goren
6fdd603ba1 added potential fix to overrun error and fifo interrupt error. test passes 2022-11-06 22:01:02 -08:00
cturek
b137a95a35 propagated otfc swap to Rad2 and 4 qslc 2022-11-06 23:32:38 +00:00
Ross Thompson
8d57e488c8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-06 17:22:25 -06:00
cturek
1e927df1a0 Added conditional OTFC swap for simplified int postprocessing 2022-11-06 23:09:09 +00:00
cturek
56b7bb3590 Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv 2022-11-06 22:40:21 +00:00
cturek
ee048325cb Added n and rightshiftx 2022-11-06 22:31:48 +00:00
cturek
67f2cb0595 p calculation 2022-11-06 22:24:21 +00:00
cturek
7567f388c2 Changed lzc names, started int/fp size merge in preproc 2022-11-06 22:21:35 +00:00
cturek
333da5c945 Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench. 2022-11-06 22:08:18 +00:00
cturek
b893d9249d Added new macros for int div preprocessing, added p, n, and rightshiftx logic 2022-11-06 21:53:48 +00:00
Kip Macsai-Goren
b42fc7ec6d fixed fifo timout handling. error now in data ready interrupt 2022-11-05 13:34:24 -07:00
David Harris
c78643f4e4 Reorder embench tests to prevent crash 2022-11-04 15:21:51 -07:00
David Harris
e57083a0ef HPTW cleanup 2022-11-04 15:21:09 -07:00
Ross Thompson
977ad1c33c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-04 13:30:08 -05:00
Kip Macsai-Goren
23268d22e5 fixed broken instructions so make works. 2022-11-03 23:06:20 +00:00
Ross Thompson
24689d6937 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-03 17:48:35 -05:00
Ross Thompson
24cb36c38d Updated to put dtb into the rodata segment for our linker script. 2022-11-03 17:48:20 -05:00
cturek
39bf6a456e renamed remOp to RemOp 2022-11-03 22:37:25 +00:00
Ross Thompson
041ab8e401 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-03 17:36:04 -05:00
Ross Thompson
34cfc01d1c Potentially a valid zero stage boot loader based on cva6. 2022-11-03 17:35:57 -05:00
cturek
890b26466f Added rem/div operation to postprocessor 2022-11-02 17:49:40 +00:00
Ross Thompson
98d4929c57 Reduced complexity of logic supressing cache operations. 2022-11-01 15:23:24 -05:00
cturek
2a45787b37 Added buffered signals for int/fp 2022-10-28 21:47:24 +00:00
Ross Thompson
f81d1e15b6 More outline for uart timeout interrupt. 2022-10-28 13:53:56 -05:00
Ross Thompson
372b9890ef Untested change to uart test for outline of how to handle rx fifo timeout. 2022-10-28 13:31:16 -05:00
cturek
2ae0a9bb5d Config Cleanup 2022-10-27 22:38:56 +00:00
Ross Thompson
03f68a4cf5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-26 14:48:50 -05:00
Ross Thompson
36d9a00471 Fixed the uart transmit fifo overrun bug. 2022-10-26 14:48:09 -05:00
cturek
51fc4de0e1 small signal cleanup 2022-10-26 18:42:49 +00:00
cturek
544c142c4f abs for int inputs 2022-10-26 16:18:05 +00:00
cturek
e401d12889 Added signed division to fdivsqrt 2022-10-26 16:13:41 +00:00
cturek
a8a89f8dfc unbroke DIVb 2022-10-26 16:11:51 +00:00
cturek
8475de128b Config cleanup 2022-10-25 21:04:09 +00:00
Jacob Pease
ec0cede2f2 Added PLIC signals for debugging on FPGA. 2022-10-25 13:57:09 -05:00
cturek
94daa961b3 Started Integer Preprocessing 2022-10-25 17:48:43 +00:00
Kip Macsai-Goren
d4dd2dcc08 Added test for UART FIFO timeout. Does not pass regression 2022-10-25 05:35:56 +00:00
Kip Macsai-Goren
8afec35db4 added additional cache stats to coremark postprocess script 2022-10-25 02:56:25 +00:00
Kip Macsai-Goren
41f9b14f69 added I cache stats to coremark output 2022-10-25 02:55:32 +00:00
Ross Thompson
2e60edaedd Added new device trees for vcu118 and vcu108 boards. 2022-10-24 17:45:10 -05:00
Ross Thompson
1510c2d92f Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
ae01c8e824 Forget to include updated xdc file. 2022-10-24 13:51:21 -05:00
Ross Thompson
cc605a1966 Bit width error. 2022-10-24 13:48:47 -05:00
Ross Thompson
857023f5de Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-24 10:12:39 -05:00
Ross Thompson
270a83352f Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks. 2022-10-23 13:46:50 -05:00
Ross Thompson
54bd1fb806 Small cleanup of interlockfsm. 2022-10-22 16:29:51 -05:00
Ross Thompson
ae7a71c0f4 Created one off test to replicate the floating point forwarding hazard bug. 2022-10-22 16:29:12 -05:00
Ross Thompson
f9a04c13df comment updates. 2022-10-22 16:28:44 -05:00