20 Commits

Author	SHA1	Message	Date
Thomas Fleming	7f7597e667	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
David Harris	865c103599	64-bit AMO debugged	2021-03-11 23:18:33 -05:00
Thomas Fleming	1294235837	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-03-11 00:15:58 -05:00
David Harris	42275e92ed	Initial untested implementation of AMO instructions	2021-03-11 00:11:31 -05:00
Noah Boorstin	2c25e270a2	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
David Harris	9c7da510fb	Created atomic test vector and directories	2021-03-08 09:38:55 -05:00
Thomas Fleming	7e11317a2d	Export SATP_REGW from csrs to MMU modules	2021-03-05 01:22:53 -05:00
Thomas Fleming	394051c02f	Begin hardware page table walker	2021-03-03 17:13:45 -05:00
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	b16846bddb	Clean up bus interface code	2021-02-26 01:03:47 -05:00
David Harris	f5e9c91193	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
David Harris	817f81c356	Debugging Bus interface	2021-02-22 13:48:30 -05:00
David Harris	37dba8fd26	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	183a2dcfb5	Debugging bus interface.	2021-02-10 01:43:54 -05:00
David Harris	2357f5513b	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	63c7c18771	Fixed lw by delaying read value by one cycle	2021-02-07 23:28:21 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	d56d7a75a6	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00