David Harris
7d857cf4bd
more TLB name touchups
2021-07-06 18:39:30 -04:00
David Harris
2e2aa2a972
connected signals in tlb by name instead of .*
2021-07-06 17:22:10 -04:00
David Harris
ee3a321002
changed tlbphysicalpagemask to structural
2021-07-06 17:16:58 -04:00
David Harris
032c38b7e7
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
2021-07-06 15:29:42 -04:00
David Harris
30fdd7abc8
Cleaned up tlb output muxing
2021-07-06 10:44:05 -04:00
David Harris
d58cad89a8
Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines
2021-07-06 10:38:30 -04:00
David Harris
694badcc6b
Created tlbcontrol module to hide details
2021-07-06 03:25:11 -04:00
David Harris
07f2064c19
Touched up TLB D and A bit checks
2021-07-04 18:17:09 -04:00
David Harris
b0f199b574
Fixed TLB_ENTRIES merge conflict and handling of global PTEs
2021-07-04 18:05:22 -04:00
David Harris
80666f0a71
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:52:00 -04:00
David Harris
8337d6df68
Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders
2021-07-04 16:33:13 -04:00
David Harris
c281539f36
TLB cleanup
2021-07-04 14:59:04 -04:00
David Harris
81742ef9e2
TLB cleanup
2021-07-04 14:37:53 -04:00
David Harris
152923e552
TLB minor organization
2021-07-04 14:30:56 -04:00
David Harris
7e22ae973e
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
1b39481a16
TLB mux and swizzling cleanup
2021-07-04 12:53:52 -04:00
David Harris
735f3b4217
Replaced generates with arrays in TLB
2021-07-04 12:32:27 -04:00
Ross Thompson
bc9c944ba0
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
David Harris
de221ff2d0
Changed physical addresses to PA_BITS in size in MMU and TLB
2021-06-18 09:11:31 -04:00
Kip Macsai-Goren
d6f47d5917
making mmu branch line up with main
2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
e209dbcf50
some cleanup of signals, not done yet
2021-06-08 13:39:32 -04:00
Kip Macsai-Goren
49515245d9
remove redundant decodes, fixed mmu logic ins/outs
2021-06-07 19:23:30 -04:00
Kip Macsai-Goren
1e174a8244
got rid of some underscores in filenames, modules
2021-06-07 18:54:05 -04:00
Kip Macsai-Goren
c96695b1b6
implemented simpler page mixers, cleaned up a bit
2021-06-07 18:32:34 -04:00
David Harris
ff62000e2c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
Kip Macsai-Goren
1ae529c450
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
Kip Macsai-Goren
5187574e8a
implemented Sv48.
2021-06-01 17:50:37 -04:00
Thomas Fleming
e27bc1cbf7
Clean up MMU code
2021-05-14 07:12:32 -04:00
Thomas Fleming
4bae666fa1
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Thomas Fleming
09c9c49541
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/pagetablewalker.sv
2021-04-13 13:42:03 -04:00
Thomas Fleming
dc8a165806
Add lru algorithm to TLB
2021-04-13 13:37:24 -04:00
Teo Ene
1018a10625
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Thomas Fleming
fc39535e4e
Refactor TLB into multiple files
2021-04-08 03:24:10 -04:00
Thomas Fleming
303c2c4839
Implement support for superpages
2021-04-08 02:44:59 -04:00
Thomas Fleming
1cbdaf1f05
Fix extraneous page fault stall
2021-04-03 21:28:24 -04:00
Thomas Fleming
fdb20ee1cf
Implement sfence.vma and fix tlb writing
2021-04-01 15:55:05 -04:00
Thomas Fleming
77b8e27205
Disable 'always-on' virtual memory
2021-03-30 22:49:47 -04:00
Thomas Fleming
7126ab7864
Complete basic page table walker
2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7597e667
Connect tlb, pagetablewalker, and memory
2021-03-18 14:35:46 -04:00
Thomas Fleming
8c97143be6
Place tlb parameters into constant header file
2021-03-05 13:35:24 -05:00
Thomas Fleming
1df7151fb6
Install tlb into ifu
2021-03-04 03:11:34 -05:00
Thomas Fleming
5f98c932bf
Move tlb into mmu directory
2021-03-04 02:39:08 -05:00
