Madeleine Masser-Frye
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d23d5d12f2
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fresh set of syntheses
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2022-06-15 18:26:16 +00:00 |
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James Stine
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d69a8f4077
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Add back SV for integer division to use 8-bit CPA in qslc
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2022-06-15 11:46:39 -05:00 |
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James Stine
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535a9a04ee
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Add r=4 C code
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2022-06-15 11:44:09 -05:00 |
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Katherine Parry
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11b252a735
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some synth fpu optimizations
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2022-06-14 23:58:39 +00:00 |
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David Harris
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ecd733942a
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Removed testbench.sv.bak
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2022-06-14 22:04:38 +00:00 |
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DTowersM
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a0d6f948b8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-14 17:08:48 +00:00 |
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DTowersM
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2023a2af2c
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fixed a typo in makefile
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2022-06-14 17:08:39 +00:00 |
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Katherine Parry
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998876ce49
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removed false critical path from fpu
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2022-06-14 16:50:46 +00:00 |
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Katherine Parry
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566001e07b
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fixed acciedental critical path in FPU
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2022-06-14 00:02:38 +00:00 |
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DTowersM
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919c1818a8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 23:34:35 +00:00 |
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DTowersM
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3d8cf0c0a7
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fixed typo in git ignore
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2022-06-13 23:34:27 +00:00 |
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DTowersM
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8178a6732b
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added back the .git ignore and .git modules for the coremark directory, also added graphGen to the main repo
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2022-06-13 23:33:10 +00:00 |
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DTowersM
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1f4d56ba32
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added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
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2022-06-13 23:23:57 +00:00 |
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Katherine Parry
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31fd8772cf
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postprocessing unit created and passing all tests
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2022-06-13 22:47:51 +00:00 |
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David Harris
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8ea484a343
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Cleanup on RAM module
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2022-06-13 19:37:43 +00:00 |
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David Harris
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b7a7ca6eac
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Typo in gpio reset
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2022-06-13 19:37:05 +00:00 |
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slmnemo
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eb41185a70
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-13 12:30:33 -07:00 |
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David Harris
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be65e8f862
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Removed SRT testvectors from repo
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2022-06-13 19:27:33 +00:00 |
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slmnemo
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915b8e2adb
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-13 12:27:23 -07:00 |
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slmnemo
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7b704f8db0
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Merge branch 'cacheburstmode' into main.
Cache burst mode is now working! It also uses the new RAM.
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2022-06-13 12:26:18 -07:00 |
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slmnemo
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98c07ce2c0
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Added more comments
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2022-06-13 12:26:08 -07:00 |
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David Harris
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ccd16210bc
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 19:26:07 +00:00 |
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David Harris
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e9ef9a5cb8
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Fixed XOR logic in GPIO
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2022-06-13 19:26:03 +00:00 |
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slmnemo
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3d715a098c
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Added comment about name of LSUBusInit/Lock signal
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2022-06-13 10:56:02 -07:00 |
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slmnemo
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cadd62e49f
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Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
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2022-06-10 20:43:56 -07:00 |
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slmnemo
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beb4317e68
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Added comments to signals added so the bus is easier to analyze
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2022-06-10 20:30:04 -07:00 |
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slmnemo
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b7357efc6b
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Fixed failed regression state by only enabling counting when doing cached operations
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2022-06-10 20:00:09 -07:00 |
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slmnemo
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63ed390c90
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Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
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2022-06-10 19:10:01 -07:00 |
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Madeleine Masser-Frye
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422bd2043f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-10 21:11:47 +00:00 |
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Madeleine Masser-Frye
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6cf37feb8d
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equation table, plot adjustments
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2022-06-10 21:11:39 +00:00 |
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Madeleine Masser-Frye
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7cdf9cd4d3
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added 'd' suffix to muxes for data-critical synths
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2022-06-10 21:11:05 +00:00 |
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DTowersM
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4bbe5eeecd
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simplified coremark
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2022-06-10 19:15:17 +00:00 |
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DTowersM
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13c1cf12b2
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added some comments to help debuggers in the future
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2022-06-10 01:44:52 +00:00 |
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slmnemo
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dc11066ff2
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Passed Regression: Seems to work perfectly fine
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2022-06-09 18:21:13 -07:00 |
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slmnemo
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ec7cdee0f3
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Merge branch 'main' into cacheburstmode
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2022-06-09 17:51:03 -07:00 |
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slmnemo
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5a6eae214a
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?
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2022-06-09 17:50:47 -07:00 |
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DTowersM
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9e2d80764d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-10 00:38:07 +00:00 |
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DTowersM
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dd34f25ffd
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changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
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2022-06-10 00:37:53 +00:00 |
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slmnemo
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3e8d3bae88
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Changes made on 9th Jun
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2022-06-09 17:33:51 -07:00 |
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slmnemo
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4ff105f18c
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Fixed lint error
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2022-06-09 17:22:04 -07:00 |
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David Harris
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c836f37a08
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New RAM for further testing
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2022-06-09 23:50:43 +00:00 |
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stineje
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470c0552f8
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Update integer division for r4 and qslc_r4a2.c
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2022-06-09 16:45:13 -05:00 |
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David Harris
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dd4fa7c682
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qslc_r4a2 generator
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2022-06-09 17:26:47 +00:00 |
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slmnemo
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0d04751c77
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Fixed error when doing uncached accesses where HTRANS was always 2
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2022-06-08 18:58:07 -07:00 |
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slmnemo
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81d373c7ab
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Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
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2022-06-08 17:34:02 -07:00 |
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Madeleine Masser-Frye
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0e64494e46
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-09 00:08:15 +00:00 |
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Madeleine Masser-Frye
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5522adc922
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restored functionality of makeCoefTable()
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2022-06-09 00:07:51 +00:00 |
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Madeleine Masser-Frye
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a58a756076
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added one bit muxes for data critical synths
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2022-06-09 00:06:12 +00:00 |
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Madeleine Masser-Frye
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310f55b6b7
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added false path for data critical muxes
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2022-06-09 00:05:38 +00:00 |
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slmnemo
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11924bdd9b
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Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending
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2022-06-08 15:59:15 -07:00 |
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