David Harris
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7c91ed38a3
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LSU minor edits
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2022-08-23 07:35:47 -07:00 |
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David Harris
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b795cf4731
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Updated testbench assertions.
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2022-08-23 07:23:24 -07:00 |
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David Harris
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a9a5285ba8
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Named HTRANS states in busfsm
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2022-08-22 13:56:46 -07:00 |
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David Harris
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24a05c35d9
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Renamed signals for LSU - FPU interface
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2022-08-22 13:47:56 -07:00 |
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David Harris
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13d863a810
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renamed GrantData to LSUGrant
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2022-08-22 13:47:19 -07:00 |
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David Harris
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34eece10b8
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Finished FPU-LSU interface cleanup
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2022-08-22 13:43:04 -07:00 |
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David Harris
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7151befd04
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Removed FStore2 and simplified HPTW
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2022-08-22 13:29:54 -07:00 |
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David Harris
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bf54c1c868
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Simplified FPU-LSU interface to skip IEU
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2022-08-22 13:29:20 -07:00 |
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David Harris
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fffad8b314
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-22 13:28:54 -07:00 |
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David Harris
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2170203847
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Simplified FPU-LSU interface to skip IEU
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2022-08-22 13:28:51 -07:00 |
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Katherine Parry
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a1f0c6c598
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-22 17:16:25 +00:00 |
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Katherine Parry
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1accb92745
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sqrt passes - lint warnings remain
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2022-08-22 17:16:12 +00:00 |
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David Harris
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564281b8c1
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Removed 2-cycle FPU-IEU latency stall
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2022-08-22 16:14:15 +00:00 |
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David Harris
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1404d1c248
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moved CSA to generic
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2022-08-22 08:41:23 +00:00 |
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David Harris
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a8870b70b2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-22 08:28:31 +00:00 |
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David Harris
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b91f33372e
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Commented out unused comparators
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2022-08-22 08:28:28 +00:00 |
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Ross Thompson
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88d34d0f56
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-21 16:03:11 -05:00 |
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Ross Thompson
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21526957cf
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
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Ross Thompson
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92c3cdc27d
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Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.
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2022-08-21 15:28:29 -05:00 |
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Ross Thompson
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a049f456e8
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Removed logic from Verilog wrapper.
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2022-08-21 14:07:43 -05:00 |
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Ross Thompson
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dad6770fc3
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Updated fpga testbench.
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2022-08-21 14:07:26 -05:00 |
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Katherine Parry
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617dc02d01
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fixed -1 issue in division
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2022-08-20 00:53:45 +00:00 |
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Ross Thompson
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96d6218078
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Possible reduction of ignorerequest.
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2022-08-19 18:07:44 -05:00 |
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Ross Thompson
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5301444a61
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Changed signal names.
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2022-08-17 16:12:04 -05:00 |
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Ross Thompson
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970a90dd72
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Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
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2022-08-17 16:09:20 -05:00 |
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Ross Thompson
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c3bd396bdb
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Removed old code from interlockfsm.
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2022-08-17 12:52:56 -05:00 |
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Katherine Parry
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0f077012c3
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sqrt tests in regression uncommented and pass
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2022-08-07 23:38:10 +00:00 |
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Katherine Parry
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8eeca3319c
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radix-2 1 copy passes testfloat
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2022-08-06 22:54:05 +00:00 |
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Katherine Parry
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8f1d8669b0
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fixed fsw problem and removed 2 bit shift from shift correction
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2022-08-03 22:16:51 +00:00 |
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David Harris
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8b8f045491
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Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
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David Harris
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62252c2167
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Debugging plic-s test
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2022-08-03 13:21:09 +00:00 |
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David Harris
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6ee8036ae7
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plic-s debug
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2022-08-03 12:33:09 +00:00 |
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David Harris
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cfa3ee4ef4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-03 03:48:11 +00:00 |
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David Harris
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e3ea86f984
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Started plic-s tests
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2022-08-03 03:48:08 +00:00 |
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Madeleine Masser-Frye
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658f2626f4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-02 16:25:25 +00:00 |
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David Harris
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b13cdf79b3
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FMA cleanup
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2022-08-02 07:42:32 -07:00 |
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David Harris
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baeafc4fd2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-02 07:34:12 -07:00 |
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David Harris
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d3e39763b6
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Moved InvA to sign block; simplified fmaexpadd coding
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2022-08-02 07:34:09 -07:00 |
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Madeleine Masser-Frye
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f39631bdf4
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changed synthesis to write modified config files in output directory
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2022-08-02 12:19:14 +00:00 |
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Madeleine Masser-Frye
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48690e6339
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edited indentation
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2022-08-02 10:23:04 +00:00 |
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Ross Thompson
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acd920ae2f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-01 22:09:11 -05:00 |
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Ross Thompson
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f7e64fcd69
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Fixed fstore2 in cache?
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2022-08-01 22:04:44 -05:00 |
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David Harris
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0482bf4fc0
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merged lza back into main
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2022-08-01 19:45:21 -07:00 |
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David Harris
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0b95ca129c
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Fixed fmaadd to work with new LZA
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2022-08-01 19:40:55 -07:00 |
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Ross Thompson
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b8356c7449
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Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
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2022-08-01 21:12:25 -05:00 |
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Ross Thompson
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171cf7413b
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Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
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2022-08-01 21:08:14 -05:00 |
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Ross Thompson
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5d9dab6149
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pulled swbbytemask out of subword write.
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2022-08-01 20:48:45 -05:00 |
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David Harris
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8b44037f58
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Parameterized fmalza
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2022-08-01 16:18:02 -07:00 |
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David Harris
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6e78b46761
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Completed LZA simplificaiton
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2022-08-01 16:13:16 -07:00 |
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David Harris
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76021769a7
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lza cleanup
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2022-08-01 16:01:02 -07:00 |
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