Ross Thompson
403daecc8e
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
Ross Thompson
b52f593ecb
Reorganized the configs.
2022-10-09 16:46:48 -05:00
David Harris
bd6f2444cd
Fixed address decoder hanging buildroot
2022-08-26 22:01:25 -07:00
David Harris
76006825b3
Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding
2022-08-26 21:18:18 -07:00
David Harris
6409548c8b
Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
2022-08-26 20:26:12 -07:00
David Harris
906f6f2990
Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
2022-08-26 20:12:03 -07:00
Ross Thompson
4ad7ccc7f7
Possible fixes for earily messup of rv32ic and rv64ic configs.
2022-08-25 14:42:08 -05:00
Ross Thompson
bd9401179d
BROKEN. Don't use this commit.
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Issue running cacheless with bus.
2022-08-25 11:02:46 -05:00
Ross Thompson
b650d7e05a
Renamed RAM to UNCORE_RAM.
2022-08-24 18:09:07 -05:00
Ross Thompson
c6927d2ace
Modified the lsu/ifu memory configurations.
2022-08-24 12:35:15 -05:00
Ross Thompson
856ac24686
Removed replay from the config files.
2022-07-24 00:34:11 -05:00
slmnemo
7c019ea074
Removed references to initialization files
2022-06-23 16:50:27 -07:00
DTowersM
dd34f25ffd
changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
2022-06-10 00:37:53 +00:00
slmnemo
65961223f8
Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files
2022-06-02 02:51:51 +00:00
David Harris
4f1b0fdc64
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
Kip Macsai-Goren
746fcfde30
set WFI timeout to after 16 bits of counting for all configs
2022-04-28 18:14:08 +00:00
Shreya Sanghai
a8b3cc8cf9
added bpred size to wally config
2022-04-18 04:21:03 +00:00
David Harris
b4902a6ff9
First implementation of WFI timeout wait
2022-04-17 17:20:35 +00:00
Katherine Parry
c3d07b2c46
generating all testfloat vectors
2022-04-04 17:17:12 +00:00
Ross Thompson
67ff8f27f4
Can now support the following memory and bus configurations.
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1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
bbracker
202bd2f8f8
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
d21be9d998
Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
2022-02-04 23:49:07 -06:00
David Harris
38bbe23d14
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
David Harris
da8819d64b
changed DMEM and IMEM configurations to support BUS/TIM/CACHE
2022-02-03 00:41:09 +00:00
David Harris
68a6b4af3d
Removed Busybear and Buildroot Configuration
2022-02-02 20:32:22 +00:00
David Harris
4ba37d5cc0
Config file & wally-riscv-arch-test cleanup
2022-02-02 16:35:52 +00:00
David Harris
748375c82f
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
Ross Thompson
a973681a90
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
aad28366d7
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
Ross Thompson
960af4b70f
Set rv32ic to not use icache.
2022-01-12 14:10:09 -06:00
Ross Thompson
06168e67e4
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
