bbracker
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13cf7c0934
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linux testbench now ignores HWRITE glitches caused by flush glitches
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2021-06-25 09:28:52 -04:00 |
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bbracker
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5b47da21ba
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made testbench-linux's PCDwrong be FlushD
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2021-06-25 08:15:19 -04:00 |
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Katherine Parry
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7e3483b283
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FPU forwarding reworked pt.1
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2021-06-24 18:39:18 -04:00 |
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bbracker
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13df69abdb
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-24 01:42:41 -04:00 |
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bbracker
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be962cb1ff
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overhauled linux testbench and spoofed MTTIME interrupt
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2021-06-24 01:42:35 -04:00 |
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Katherine Parry
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8eed89616c
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fpu clean-up
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2021-06-23 16:42:40 -04:00 |
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Katherine Parry
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353a27f12f
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rv64f FLW passes imperas tests
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2021-06-22 16:36:16 -04:00 |
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David Harris
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7930c2ebb4
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Commented out 100k tests to improve speed
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2021-06-21 01:43:18 -04:00 |
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David Harris
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1ec90a5e1f
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Reversed [0:...] with [...:0] in bus widths across the project
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2021-06-21 01:17:08 -04:00 |
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bbracker
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bf3c2dc089
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-20 22:29:40 -04:00 |
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bbracker
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3000c27acd
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linux actually uses FPU now!
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2021-06-20 22:29:21 -04:00 |
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Katherine Parry
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2b67f25683
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all rv64f instructions except convert, divide, square root, and FLD pass
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2021-06-20 20:24:09 -04:00 |
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bbracker
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2643130c41
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read from MSTATUS workaround because QEMU has incorrect MSTATUS
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2021-06-20 10:11:39 -04:00 |
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bbracker
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14ae87ff0a
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testbench update b/c QEMU extends 32b CSRs to 64b
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2021-06-20 09:24:19 -04:00 |
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bbracker
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c77aabdc6f
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make buildroot ignore SSTATUS because QEMU did not originally log it
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2021-06-20 05:31:24 -04:00 |
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bbracker
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918ff5093a
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MSTATUS workaround
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2021-06-20 04:48:09 -04:00 |
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bbracker
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069a79fafd
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workaround for ignoring MTIME
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2021-06-20 02:26:39 -04:00 |
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bbracker
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d62d9a7aac
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make buildroot waves only turn on after a user-specified point
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2021-06-20 00:39:30 -04:00 |
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bbracker
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8d242d73b5
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fixed PCtext error by using blocking assignments
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2021-06-18 17:37:40 -04:00 |
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bbracker
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03a45aeef1
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restore graphical buildroot sim
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2021-06-18 11:58:16 -04:00 |
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bbracker
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faae30c31c
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remove unused testbench-busybear.sv
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2021-06-18 08:15:19 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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336936cc39
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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bbracker
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5b96f7fbd7
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making linux waveforms more useful
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2021-06-17 08:37:37 -04:00 |
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bbracker
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b459d0cc80
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changed parsedCSRs2] to parsedCSRs
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2021-06-17 05:18:14 -04:00 |
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David Harris
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01d6ca1e2a
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Fixed lint WIDTH errors
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2021-06-09 20:58:20 -04:00 |
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David Harris
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b613f46c2d
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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bbracker
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cc91c774a6
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Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
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2021-06-08 12:41:25 -04:00 |
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bbracker
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e7e4105931
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* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
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2021-06-08 12:32:46 -04:00 |
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Kip Macsai-Goren
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c96695b1b6
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implemented simpler page mixers, cleaned up a bit
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2021-06-07 18:32:34 -04:00 |
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David Harris
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2ae5ca19b5
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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dc0b19dfaa
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Katherine Parry
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75a6097467
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fixed lint warnings for fpu and lzd
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2021-06-05 12:06:33 -04:00 |
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Kip Macsai-Goren
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22e8e06ac7
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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Katherine Parry
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fc65aedbd6
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Double-precision FMA instructions
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2021-06-04 14:00:11 -04:00 |
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Kip Macsai-Goren
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1ea9b94cf1
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added tests for SV48 and translation off with vmem
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2021-06-03 14:28:52 -04:00 |
|
James E. Stine
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2eeb12c674
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Updates to muldiv.sv for 32-bit div/rem
|
2021-06-01 15:31:07 -04:00 |
|
Ross Thompson
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89ad4477e4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-06-01 11:33:12 -05:00 |
|
Ross Thompson
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857f59ab5c
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Now have global history working correctly.
|
2021-06-01 10:57:43 -05:00 |
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James E. Stine
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ddbdd0d5a2
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Modify muldiv.sv to handle W instructions for 64-bits
|
2021-05-31 23:27:42 -04:00 |
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bbracker
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39ae743543
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
|
2021-05-28 23:11:37 -04:00 |
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Katherine Parry
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778ba6bbf5
|
classify unit created and passes imperas tests
|
2021-05-27 18:53:55 -04:00 |
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Katherine Parry
|
1459d840ed
|
All compare instructions pass imperas tests
|
2021-05-27 15:23:28 -04:00 |
|
Katherine Parry
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309e6c3dc1
|
FADD and FSUB imperas tests pass
|
2021-05-26 12:33:33 -04:00 |
|
Kip Macsai-Goren
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8ae43a15d4
|
partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
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2021-05-24 20:59:26 -04:00 |
|
James E. Stine
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295263e122
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Mod for DIV/REM instruction and update to div.sv unit
|
2021-05-24 19:29:13 -05:00 |
|
Ross Thompson
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c5310e85c1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-24 14:28:41 -05:00 |
|
Katherine Parry
|
90d5fdba04
|
FMV.X.D imperas test passes
|
2021-05-24 14:44:30 -04:00 |
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