Katherine Parry
6baded9121
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
slmnemo
054cf5f7b0
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
284e0395a0
Merge branch 'main' into cacheburstmode
2022-06-08 02:21:33 +00:00
slmnemo
2d76953d42
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
73e0c1c07f
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
David Harris
c7ec9282fe
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
slmnemo
847c7930c4
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
08430a1e85
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
slmnemo
8c8a7daec2
Fixed grammar on two comments in bpred.sv
2022-05-16 22:41:18 +00:00
David Harris
ce24c080d5
More unused signal cleanup
2022-05-12 15:26:08 +00:00
David Harris
5670f77de2
More unused signal cleanup
2022-05-12 15:21:09 +00:00
David Harris
1a7599ce94
Changed WFI to stall pipeline in memory stage
2022-05-05 02:03:44 +00:00
Kip Macsai-Goren
bd87af478a
Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
2022-04-22 22:46:11 +00:00
David Harris
eaa0d44980
Fixed WFI decoding in IFU
2022-04-18 19:02:08 +00:00
Shreya Sanghai
6f0085201b
replaced k with bpred size
2022-04-18 04:21:03 +00:00
David Harris
0932d4df46
Added WFI support to IFU to keep it in the pipeline
2022-04-14 17:26:17 +00:00
Ross Thompson
396f697d2f
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
bbracker
69a0f6e00b
big interrupts refactor
2022-03-30 13:22:41 -07:00
Ross Thompson
e4f4e1bd43
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-30 11:09:44 -05:00
David Harris
c4f2c6b110
fpu compare simplification, minor cleanup
2022-03-29 17:11:28 +00:00
Ross Thompson
fe896bff8e
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
Ross Thompson
ee4b38dce3
dtim writes are supressed on non cacheable operation.
2022-03-12 00:46:11 -06:00
Ross Thompson
67ff8f27f4
Can now support the following memory and bus configurations.
...
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
Ross Thompson
9dce2a0679
Towards allowing dtim + bus.
2022-03-11 14:58:21 -06:00
Ross Thompson
b7a680ec2a
Moved subcachelineread inside the cache. There is some ugliness to still resolve.
2022-03-11 12:44:04 -06:00
Ross Thompson
a18f06c20b
Moved subcacheline read inside the cache.
2022-03-11 11:03:36 -06:00
Ross Thompson
52cc852600
removed unused parameter.
2022-03-11 10:43:54 -06:00
Ross Thompson
6d914def08
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
396c97fc36
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
Ross Thompson
7a129c75cd
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
David Harris
bc2b757952
bit write update
2022-03-09 19:09:20 +00:00
David Harris
27f09ffb33
Refactored SRAM bit write enable
2022-03-09 17:49:28 +00:00
Ross Thompson
3ec32d7ce8
Removed unused signal.
2022-03-08 16:58:26 -06:00
Ross Thompson
d78ba777a4
Added parameter to spillsupport.
2022-03-08 16:38:48 -06:00
Ross Thompson
7b96b3f73c
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
Ross Thompson
730fdb029a
Fixed bug with DAPageFault being wrong when HPTW writes not supported.
2022-02-23 10:54:34 -06:00
Ross Thompson
6f53f7943f
More spillsupport more structual.
2022-02-23 10:27:14 -06:00
Ross Thompson
19ec874641
Fixed bug with spill support and Instruction DA Page Faults.
2022-02-23 10:16:12 -06:00
Ross Thompson
15f6871a8d
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
59f04f2518
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
8a280f211f
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
beac362364
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01
cleanup of signal names.
2022-02-16 15:29:08 -06:00
David Harris
1d5c8a7b98
t push
...
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
David Harris
b360e7b941
Synthesis cleanup
2022-02-12 06:25:12 +00:00
Ross Thompson
febd019854
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
6d12010d02
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
