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129 Commits

Author SHA1 Message Date
Ross Thompson
d887124837 Found a bug where the d and i cache misses were not recorded in the performance counters. 2023-02-20 16:00:29 -06:00
Ross Thompson
1982c66b72 Simiplified BTB. 2023-02-20 15:39:42 -06:00
David Harris
bdcd867c11 Removed test code that broke LSU 2023-02-20 12:42:46 -08:00
David Harris
c6c21463d9 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-20 11:28:15 -08:00
David Harris
081a817925
Merge pull request #98 from ross144/main 
New gshare implementation
 2023-02-20 11:27:47 -08:00
David Harris
023ba68088 Extraction script updates to match new reports names 2023-02-20 10:16:45 -08:00
David Harris
df9950483e Removed unused and incomplete ROM macro instantations 2023-02-20 05:59:57 -08:00
David Harris
a59526fc8e Fixed IROM size parameters 2023-02-20 05:32:43 -08:00
David Harris
1d3b41e0fb New expression for BTB_SIZE to avoid error during sky90 synthesis 2023-02-20 04:02:00 -08:00
Ross Thompson
2d417c33a4 Simplified BTB by removing the valid bit. the instruction class provides the equivalent information. 2023-02-19 23:53:20 -06:00
Ross Thompson
0d79c0cebe Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-19 22:54:27 -06:00
Ross Thompson
b32093b33b Simplified branch predictor. 2023-02-19 22:49:48 -06:00
David Harris
0ac9c9e62a Added BTB_SIZE parameter independent of BPRED_SIIZE 2023-02-19 20:13:50 -08:00
David Harris
5b197f4f9d Parameterized btb to depend on BPRED_SIZE 2023-02-19 19:59:07 -08:00
David Harris
06872e3822 Adjusted DTIM to always be 512B independent of XLEN 2023-02-19 16:14:38 -08:00
David Harris
5b8d1e4134 PMP checker size check to avoid spurious warnings 2023-02-19 16:08:23 -08:00
David Harris
ac21bed64d Moved conditional instantiation outside pmpchecker 2023-02-19 15:31:00 -08:00
David Harris
7d031fcae0 Disabled W64M register for RV32 2023-02-19 07:03:31 -08:00
David Harris
6d405ad69b Fixed RAM instantiations 2023-02-19 06:31:41 -08:00
Ross Thompson
9ee48637dc Possibly much better branch predictor implemention. 
The complexity is significantly reduced.
 2023-02-19 00:17:37 -06:00
Ross Thompson
d44cb1febb Minor fix. 2023-02-18 23:55:46 -06:00
David Harris
0eda753dc4 Removed unused PredInstrClassE register from bpred 2023-02-18 05:59:25 -08:00
David Harris
0f4226a950 Removed unused weq0M register fron fdivsqrtpostproc 2023-02-18 05:57:39 -08:00
David Harris
66e5c60fb4 Fixed issue #57 of sign selection for improperly NaN-boxed number 2023-02-18 05:34:40 -08:00
David Harris
5986931fdc Fixed unpacking of illegal NaN box. Fixed issue #56 of sign injection NaN 2023-02-18 05:25:38 -08:00
David Harris
dc19f8a8ec Created PostBox signal to NaN-box malformed NaNs of excess length. Fixes Issue #55 2023-02-17 20:51:43 -08:00
David Harris
a194740562 Fixed RAM bugs and refactored with read taking place after clock edge rather than before. 2023-02-17 19:14:38 -08:00
David Harris
9275bfb839 Memory synthesis updates 2023-02-17 15:33:49 -08:00
David Harris
2060683770 Continue fixing memory macros for synthesis 2023-02-17 15:15:37 -08:00
Ross Thompson
0cacfbd322 Renamed globalhistory predictor. 2023-02-17 16:08:34 -06:00
Ross Thompson
2f1bebfd57 Fixed global history predictor. 2023-02-17 16:05:48 -06:00
Ross Thompson
a95be0b567 More updates. 2023-02-17 15:53:49 -06:00
Ross Thompson
df4a27a2e3 Updated global history predictor. 2023-02-17 15:53:15 -06:00
David Harris
3523318acb Synthesis with memories 2023-02-17 13:51:05 -08:00
Ross Thompson
0d271130b9 Fixed a branch predictor performance issue. 2023-02-17 15:37:03 -06:00
Ross Thompson
5d5e4580d4 Merge branch 'main' of github.com:ross144/cvw 2023-02-17 10:58:16 -06:00
Ross Thompson
a325adf1be Fixed bug with branch predictor. 2023-02-17 10:57:50 -06:00
David Harris
c3cc2f98d6 Reverted lab3 changes in dev branch 2023-02-16 18:10:05 -08:00
David Harris
5fef9de80e Merge branch 'lab3_2023' of https://github.com/openhwgroup/cvw into dev 2023-02-16 17:57:51 -08:00
David Harris
532abb5b95
Update datapath.sv 2023-02-16 17:53:31 -08:00
David Harris
6527257305
Update controller.sv 2023-02-16 17:52:44 -08:00
David Harris
685d3ff568
Update alu.sv 2023-02-16 17:52:25 -08:00
Ross Thompson
27f6552315 keep this commit off of cvw. 2023-02-16 11:05:24 -06:00
David Harris
d83c61cafc Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass. 2023-02-16 07:37:12 -08:00
James Stine
744991bd5a Update if-then-else for ram items 2023-02-15 18:12:12 -06:00
Ross Thompson
69472b8145 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-15 11:29:39 -06:00
Ross Thompson
094b307724 Merge branch 'main' of github.com:ross144/cvw 2023-02-13 18:54:07 -06:00
Ross Thompson
9c9acc0055 Updated gshare (no speculation) to have better performance. 2023-02-13 18:52:52 -06:00
Ross Thompson
33d2bf84f8 More fixeds to global history. 2023-02-13 18:08:51 -06:00
Ross Thompson
a579bbcdd1 Fixed global history predictor. 2023-02-13 18:08:13 -06:00
Ross Thompson
bbc6095260 Updated global history predictor. 2023-02-13 18:07:32 -06:00
Ross Thompson
9f25b53b36 Fixed bug in basic gshare implementation. Should be a better comparison to the speculative versions now. 2023-02-13 17:57:05 -06:00
Ross Thompson
b298a8afc5 Created copy of gshare. I think there may be a simpler implementation. 2023-02-13 17:29:51 -06:00
Ross Thompson
a80dbd3aec Further branch predictor improvements. 2023-02-13 17:23:56 -06:00
Ross Thompson
717cba270c Partial improvement. 2023-02-13 17:10:24 -06:00
Ross Thompson
f4af38a004 Hacked commit. Fixes the gshare bugs introduced last week. 
Need to recover the good changes in the next commit.
 2023-02-13 16:14:17 -06:00
Ross Thompson
1d74663f42 Partial fix for gshare bugs from the last two weeks. 2023-02-13 11:57:25 -06:00
Ross Thompson
58749a8c57 Removed another bit from btb class. 2023-02-12 11:33:43 -06:00
Kevin Kim
c59dfc1e30
fixed typo in LZC 2023-02-11 19:59:03 -08:00
Ross Thompson
1e0667db1d More simplifications to the BP. 2023-02-10 17:09:35 -06:00
Ross Thompson
9c4da7381f Experimental branch prediction optimization. 2023-02-10 15:45:56 -06:00
Ross Thompson
9c2e0de672 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-10 10:38:39 -06:00
Ross Thompson
c229f0064e Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic. 2023-02-10 10:33:10 -06:00
Ross Thompson
282ffd1313 RAS and RAS documentation now consistent. 2023-02-10 09:06:51 -06:00
Ross Thompson
faf7cd8c8a Updated globalhistory predictor. 2023-02-09 14:48:02 -06:00
Ross Thompson
996bb289d3 Simplified branch predictor. 2023-02-08 18:24:38 -06:00
David Harris
5bf709d7c3 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-07 16:49:58 -08:00
Ross Thompson
7263fab4b1 Branch predictor cleanup. 2023-02-07 14:01:59 -06:00
David Harris
195e7c1a9c Moved STATUS_FS_INT write to if statement to properly prioritize 2023-02-07 06:55:42 -08:00
David Harris
0712fa8f67 Disabled STATUS_FS at reset, fixing issue #71 2023-02-07 06:31:14 -08:00
Ross Thompson
54a128491e Fixed Bug 66. 
If a load missed at the same time as a spilled instruction fetch with an ITLB miss in the second cache line, the HPTW did not wait for the load miss to finish.
 2023-02-06 17:32:28 -06:00
Ross Thompson
a33c579e4b Removed unreachable if branch in hptw next state logic. 2023-02-06 16:42:07 -06:00
David Harris
103781923e Parenthesized reduction operators to avoid DC lint 2023-02-04 18:49:47 -08:00
David Harris
1bb5599806 Developing debug test 2023-02-04 08:31:47 -08:00
David Harris
b13087e706 Fixed merge issues on synthDC PR 2023-02-04 04:13:40 -08:00
David Harris
e0915acad9 Improved illegal NaN-box detection and formatted fsgninj 2023-02-04 03:42:20 -08:00
David Harris
d7ae05ae8e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-03 08:36:11 -08:00
David Harris
aae035226f Merged with memories 2023-02-02 14:50:46 -08:00
David Harris
99d179dd3e Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00