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69674f272a
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Author SHA1 Message Date
Ross Thompson
69674f272a We now have a rough sdc read routine. 2021-09-25 17:51:38 -05:00
Ross Thompson
10b46981ff Updated ignore file. 2021-09-24 18:48:45 -05:00
Ross Thompson
23425c8d71 Write of the SDC address register is correct. The command register is not yet working. 
The root problem is the command register needs to be reset at the end of the SDC transaction.
 2021-09-24 18:48:11 -05:00
Ross Thompson
86524a5f64 Now have software interacting with the initialization and settting the address register. 2021-09-24 18:30:26 -05:00
Ross Thompson
44196af61a Have program which checks for sdc init and issues read, but read done is 
not correctly being read back by the software.  The error is in how the
sdc indicates busy.
 2021-09-24 15:53:38 -05:00
Ross Thompson
17c62b7d5a Fixed lint errors in the SDC. 2021-09-24 12:38:48 -05:00
Ross Thompson
4f7bc1be48 Added either the sdModel or constant driver for the SDC ports in all test benches. 2021-09-24 12:31:51 -05:00
Ross Thompson
80e37d2291 Added SDC defines to each config mode. 
Added sd_top which is the sd card reader.
 2021-09-24 12:24:30 -05:00
Ross Thompson
9fdb1d3cc9 setup so the sdc does not need to load a model in the imperas test bench. 2021-09-24 11:30:52 -05:00
Ross Thompson
c644e940c2 Updated Imperas test bench to work with the SDC reader. 2021-09-24 11:22:54 -05:00
Ross Thompson
fea439b84d SDC to ABHLite interface partially done. 
Added SDC to adrdec and uncore.
 2021-09-24 10:45:09 -05:00
Ross Thompson
92ea88c57b Added clock gater and divider to generate the SDCCLK. 2021-09-23 17:58:50 -05:00
Ross Thompson
3cbbd15763 Partial implementation of SDC AHBLite interface. 2021-09-23 17:45:45 -05:00
Ross Thompson
3473f1e612 Started the AHBLite to SDC interface. 2021-09-22 18:08:38 -05:00
Ross Thompson
ec0d2bc7d7 Initial SD Card reader. 2021-09-22 10:50:29 -05:00
Ross Thompson
221dbe92b2 Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
Ross Thompson
e16c27225b Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00
Ross Thompson
cfd522da6b The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
Ross Thompson
0b1e59d075 Updated Dcache to fully support flush. This appears to work. 
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
 2021-09-17 10:25:21 -05:00
Ross Thompson
615fd41e7b Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
348187ea70 Added counters to walk through d cache flush. 2021-09-16 17:12:51 -05:00
Ross Thompson
d901f60a6d Added flush controls to cachway. 2021-09-16 16:56:48 -05:00
Ross Thompson
cae350abb7 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
bbracker
a158558b83 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-15 17:31:11 -04:00
bbracker
ff5379fd95 fix regression 2021-09-15 17:30:59 -04:00
David Harris
9ae25b0cea Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
bbracker
ee1503a249 created script to determine which functions are most frequently used 2021-09-14 19:41:05 -04:00
bbracker
2738e9c900 IRQ timing template 2021-09-13 18:48:28 -04:00
David Harris
92385a1d51 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-13 12:41:07 -04:00
David Harris
9fa048980d Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
Ross Thompson
cd6d1e0b12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-13 09:41:34 -05:00
David Harris
7be1160a48 Cleaned up wally-arch test scripts 2021-09-13 00:02:32 -04:00
David Harris
bbb6c7bef7 Restored old integer divider 2021-09-12 22:07:52 -04:00
Ross Thompson
296da4f437 FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
David Harris
dd1e7548ed Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
Ross Thompson
be864abcc5 Fixed bug with or_rows. 
If ROWS == 1 then the output was always X.  Fixed by adding if to check if ROWS==1.
 2021-09-11 15:51:11 -05:00
Ross Thompson
570aab4275 Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches. 2021-09-11 15:40:27 -05:00
Ross Thompson
5744796431 Fixed dcache to prevent latches in FPGA synthesized design. 2021-09-11 12:03:48 -05:00
Ross Thompson
6f4542f063 Third attempt at fixing the write enables for the icache cacheway. 2021-09-09 15:08:10 -05:00
Ross Thompson
6965bde95c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Refixed some bit width issues in the icache.
 2021-09-09 12:44:02 -05:00
Ross Thompson
1d370ca71f fixed some lint bugs. 2021-09-09 12:38:57 -05:00
bbracker
4a17af5b7c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-09 13:22:31 -04:00
bbracker
3a520cb540 changed fix_mem to not use hardcoded file names 2021-09-09 13:22:24 -04:00
David Harris
12bd351edf Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
David Harris
9480f8efdb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-08 16:00:12 -04:00
David Harris
118cb7fb87 Added testbench-arch for riscv-arch-test suite 2021-09-08 15:59:40 -04:00
Ross Thompson
86fbe2a654 Changed configs to support 4 ways set associative caches. 2021-09-08 12:52:49 -05:00
Ross Thompson
6550f38af9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-08 12:47:03 -05:00
Ross Thompson
a15d6c1c96 Slight modification to wave file. 2021-09-08 10:40:46 -05:00
bbracker
bb84354a47 fixed bug where M mode was sensitive to S mode traps 2021-09-07 19:14:39 -04:00