Kip Macsai-Goren
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5fe8b08253
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Merge remote-tracking branch 'upstream/main' into bit-manip
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2023-03-03 09:36:44 -08:00 |
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David Harris
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17adba5fd5
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Merge pull request #124 from ross144/main
Added additional performance counters. Ch 5 is update todate with these changes.
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2023-03-03 06:15:49 -08:00 |
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Ross Thompson
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baab2cd1f0
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-03 00:22:27 -06:00 |
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Ross Thompson
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7dd8fa16c1
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Renamed BTB misprediction to BTA.
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2023-03-03 00:18:34 -06:00 |
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Ross Thompson
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bdab2c8506
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Added divide cycle counter.
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2023-03-02 23:59:52 -06:00 |
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Ross Thompson
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4b501f6e03
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Added the i and d cache cycle counters.
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2023-03-02 23:54:56 -06:00 |
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Ross Thompson
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b19d51b6a2
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Added fence counter.
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2023-03-02 23:29:20 -06:00 |
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Ross Thompson
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3dbfa96aef
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Added csr write counter, sfence vma counter, interrupt counter, and exception counter.
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2023-03-02 23:21:29 -06:00 |
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Ross Thompson
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cf4d8e6bd0
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Added store stall to performance counters.
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2023-03-02 23:10:54 -06:00 |
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Ross Thompson
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e257ec96ac
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Reordered performance counters and added space for new ones.
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2023-03-02 23:04:31 -06:00 |
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Ross Thompson
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983e30dcb1
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Fixed bug in performance counter script.
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2023-03-02 22:32:13 -06:00 |
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Ross Thompson
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9bac643db2
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Added support for branch target buffer stats.
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2023-03-02 22:16:30 -06:00 |
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Ross Thompson
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4b6a40857d
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Merge pull request #123 from eroom1966/main
fix the memory map privileges in the REF model view
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2023-03-02 09:27:35 -06:00 |
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eroom1966
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1169567219
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fix the memory map privileges in the REF model view
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2023-03-02 15:25:27 +00:00 |
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Ross Thompson
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3d1ffac7d7
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Cleaned up branch predictor performance counters.
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2023-03-01 17:05:42 -06:00 |
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David Harris
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367f058048
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Merge pull request #121 from ross144/main
Branch predictor cleanup. Chapter 10 now matches the hardware
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2023-03-01 09:57:59 -08:00 |
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Ross Thompson
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a61f8bc4cf
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Set bp to use instruction class prediction by default.
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2023-03-01 11:52:42 -06:00 |
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Ross Thompson
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e8744684cd
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Branch predictor cleanup.
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
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2023-03-01 11:24:24 -06:00 |
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Ross Thompson
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08a1153ae9
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More btb cleanup.
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2023-03-01 10:47:00 -06:00 |
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Ross Thompson
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dd2433f7ff
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Minor fix to btb.
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2023-03-01 10:45:40 -06:00 |
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Ross Thompson
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e13ba72c61
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-01 10:04:13 -06:00 |
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Ross Thompson
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64b8b0ea21
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Merge pull request #119 from eroom1966/main
update ImperasDV testbench for memory privileges
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2023-03-01 09:50:00 -06:00 |
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Ross Thompson
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8fe750148e
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Merge pull request #118 from davidharrishmc/dev
Pulled to latest commit of riscv-arch-test
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2023-03-01 09:49:19 -06:00 |
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eroom1966
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72b92e8c0d
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update testbench for memory privileges
also update configuration to define value of mimpid
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2023-03-01 15:37:11 +00:00 |
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Ross Thompson
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2773048bd4
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Name cleanup.
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2023-02-28 17:48:58 -06:00 |
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David Harris
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bd6a1dcf40
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Pulled to latest commit of riscv-arch-test
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2023-02-28 15:03:59 -08:00 |
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Kip Macsai-Goren
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9e52ede0cd
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Merge remote-tracking branch 'upstream/main' into bit-manip
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2023-02-28 14:41:51 -08:00 |
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Kip Macsai-Goren
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2cab4a2f0a
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Merge remote-tracking branch 'origin' into bit-manip
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2023-02-28 14:39:57 -08:00 |
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Ross Thompson
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87013ccaf0
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Found the performance bug with the branch predictor btb power saving update.
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2023-02-28 15:57:34 -06:00 |
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Ross Thompson
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8af61c0cc0
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Name changes to reflect diagrams.
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2023-02-28 15:37:25 -06:00 |
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Ross Thompson
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a823d8d021
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Undid the btb update as it reduces performance.
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2023-02-28 15:21:56 -06:00 |
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Kevin Kim
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036cad71c6
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bitmanip decoder spits out regwrite, w64, and aluop signals [NEEDS DEBUG]
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2023-02-28 12:09:35 -08:00 |
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Kevin Kim
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6835a635cc
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added BRegWrite, BW64, BALUOp signals to bctrl and controller
-TODO: Main decode in bmuctrl must assert these 3 signals
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2023-02-28 11:54:10 -08:00 |
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Kevin Kim
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82059fba67
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changed shifter source select signal name
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2023-02-28 11:41:40 -08:00 |
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Kevin Kim
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30ef1ac9e3
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rename result back to ALUResult in ALU
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2023-02-28 07:27:34 -08:00 |
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Ross Thompson
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3261f31e88
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This icpred and btb changes are causing a performance issue.
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2023-02-27 20:00:50 -06:00 |
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Ross Thompson
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69e8358639
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Modified the BTB to save power by not updating when the prediction is unchanged.
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2023-02-27 17:37:29 -06:00 |
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Ross Thompson
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44361f0a34
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-27 09:48:03 -06:00 |
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Ross Thompson
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1f10092f8f
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Merge pull request #117 from davidharrishmc/dev
ZMMUL support and MMU cleanup
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2023-02-27 09:46:40 -06:00 |
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David Harris
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5c8fee127b
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Added support for ZMMUL
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2023-02-27 07:29:53 -08:00 |
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Ross Thompson
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a81cc883e9
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Signal name changes.
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2023-02-27 00:39:19 -06:00 |
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David Harris
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0d3d499940
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hptw typo fix
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2023-02-26 19:38:34 -08:00 |
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Ross Thompson
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447f6b1443
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Branch predictor cleanup.
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2023-02-26 21:28:36 -06:00 |
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David Harris
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907fbfec38
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Simplified Access fault logic in HPTW
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2023-02-26 18:50:37 -08:00 |
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David Harris
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fa5be45dcd
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-26 18:35:14 -08:00 |
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David Harris
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d3f5708ded
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StoreAmo faults are generated instead of load faults on AMO operations
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2023-02-26 18:35:10 -08:00 |
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Ross Thompson
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3804626166
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Create module for instruction class prediction and decoding.
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2023-02-26 20:20:30 -06:00 |
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Ross Thompson
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86f611577f
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2023-02-26 19:58:24 -06:00 |
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David Harris
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d2fd34efe6
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Renamed DAPageFault to UpdateDA
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2023-02-26 17:51:45 -08:00 |
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David Harris
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246deeda82
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renamed UpperBitsUnequalPageFault to UpperBitsUnequal
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2023-02-26 17:32:34 -08:00 |
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