Ross Thompson
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5eb1fff27d
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Have a rough working multi manager!
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2022-08-29 17:11:27 -05:00 |
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Ross Thompson
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4f40bd07c3
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Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu.
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2022-08-29 17:04:53 -05:00 |
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Ross Thompson
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4d7b905806
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Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.
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2022-08-29 13:01:24 -05:00 |
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David Harris
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352bf88ac0
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FIxed wallypipelinedsoc merge conflict
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2022-08-25 15:36:47 -07:00 |
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David Harris
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b96942e84c
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Removed delayed AHB signals from top level
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2022-08-25 15:34:14 -07:00 |
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Ross Thompson
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109bcd470e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 16:01:02 -05:00 |
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David Harris
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6222e15946
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Extended HADDR to PA_BITS
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2022-08-25 13:11:36 -07:00 |
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Ross Thompson
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502eb0f5d1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 14:40:52 -05:00 |
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David Harris
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5dc4fb757a
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Continued busdp/ebu simplification
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2022-08-25 10:20:02 -07:00 |
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David Harris
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24ce72f0a2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 09:52:49 -07:00 |
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David Harris
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89860588b8
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Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
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2022-08-25 09:52:08 -07:00 |
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Ross Thompson
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bd9401179d
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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Ross Thompson
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5cc4f1f1cd
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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Ross Thompson
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1e1646da90
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Added generate around ebu.
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2022-08-25 09:24:13 -05:00 |
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David Harris
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8d48ff4e63
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Fixed FPU-IEU forwarding stall
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2022-08-23 14:14:41 -07:00 |
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David Harris
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113258a0d0
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Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
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2022-08-23 12:17:19 -07:00 |
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David Harris
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24a05c35d9
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Renamed signals for LSU - FPU interface
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2022-08-22 13:47:56 -07:00 |
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David Harris
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7151befd04
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Removed FStore2 and simplified HPTW
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2022-08-22 13:29:54 -07:00 |
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Ross Thompson
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a049f456e8
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Removed logic from Verilog wrapper.
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2022-08-21 14:07:43 -05:00 |
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Ross Thompson
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5d9dab6149
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pulled swbbytemask out of subword write.
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2022-08-01 20:48:45 -05:00 |
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Katherine Parry
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2ada8a8bc1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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Katherine Parry
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ca4fe08fd9
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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David Harris
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381f3298d8
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Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
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2022-07-08 09:09:02 +00:00 |
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David Harris
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2f342c430e
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fixing port errors
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2022-07-07 21:57:10 +00:00 |
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David Harris
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d73645944f
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APB CLINT passing regression
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2022-07-05 15:51:35 +00:00 |
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Katherine Parry
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6baded9121
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added rv32 double precision stores - untested
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2022-06-28 21:33:31 +00:00 |
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Katherine Parry
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254ebf478e
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added fld in rv32 - needs testing
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2022-06-20 22:53:13 +00:00 |
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Katherine Parry
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31fd8772cf
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postprocessing unit created and passing all tests
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2022-06-13 22:47:51 +00:00 |
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slmnemo
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054cf5f7b0
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Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
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2022-06-08 15:03:15 -07:00 |
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slmnemo
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284e0395a0
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Merge branch 'main' into cacheburstmode
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2022-06-08 02:21:33 +00:00 |
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slmnemo
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2d76953d42
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Added lock signal to ensure AHB speaks with the right bus
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2022-06-08 02:19:21 +00:00 |
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slmnemo
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73e0c1c07f
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Reworked bus to handle burst interfacing
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2022-06-07 11:22:53 +00:00 |
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David Harris
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1d8bc2dc1b
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Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit
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2022-06-02 09:37:59 -07:00 |
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David Harris
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c7ec9282fe
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Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
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2022-06-02 14:18:55 +00:00 |
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slmnemo
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847c7930c4
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added LSUBurstDone signal to signal when a burst has finished
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2022-05-26 16:29:13 -07:00 |
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slmnemo
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08430a1e85
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added burst size signals to the IFU, EBU, LSU, and busdp
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2022-05-25 18:02:50 -07:00 |
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David Harris
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ce24c080d5
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More unused signal cleanup
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2022-05-12 15:26:08 +00:00 |
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David Harris
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5670f77de2
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More unused signal cleanup
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2022-05-12 15:21:09 +00:00 |
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David Harris
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e2e63ca9a8
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Clean up unused signals
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2022-05-12 14:49:58 +00:00 |
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David Harris
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8166fd772e
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Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
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2022-05-11 15:08:33 +00:00 |
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David Harris
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137b411bea
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Removed M suffix from interrupts because they are generated asynchronously to pipeline
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2022-05-11 14:41:55 +00:00 |
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David Harris
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4f1b0fdc64
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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David Harris
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a516f89f22
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WFI terminates when an interrupt is pending even if interrupts are globally disabled
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2022-05-08 04:30:46 +00:00 |
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David Harris
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412d4656ed
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Zero'd wfiM when ZICSR not supported to fix hang in E tests
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2022-05-05 15:32:13 +00:00 |
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David Harris
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1a7599ce94
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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David Harris
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1166c40059
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FPU generates illegal instruction if MSTATUS.FS = 00
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2022-05-03 11:56:31 +00:00 |
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Kip Macsai-Goren
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bd87af478a
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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
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2022-04-22 22:46:11 +00:00 |
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Ross Thompson
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2376d66ec2
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Added more ILA signals.
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2022-04-02 16:39:45 -05:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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bbracker
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8ea25e591b
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fix typo that Madeleine found
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2022-03-28 15:39:29 -07:00 |
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