David Harris
4365c99b52
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
Ross Thompson
fa19a111c6
Hazard cleanup.
2022-12-15 10:05:17 -06:00
Ross Thompson
e774dd2db9
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
2022-12-15 09:53:35 -06:00
Ross Thompson
1ba1bed0b0
Broken dont' use.
2022-12-11 23:24:01 -06:00
Ross Thompson
0716aedbd5
Removed unused flushf.
2022-12-11 16:28:11 -06:00
David Harris
9395414df3
Renamed FPUStallD to FCvtIntStallD
2022-12-02 11:55:23 -08:00
David Harris
9c1b7e53e4
FPU divider working with execute stage stall
2022-12-02 11:11:53 -08:00
David Harris
4e5f62a5c1
code cleanup
2022-12-01 08:15:48 -08:00
Ross Thompson
3ac6514856
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
2022-11-13 12:25:22 -06:00
David Harris
0502b8ea4d
Comments about division hazards
2022-11-13 04:17:37 -08:00
Ross Thompson
42c0a10d07
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
611ea6882d
Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.
2022-10-22 16:27:20 -05:00
Ross Thompson
a7ae593a68
Possible fix for interrupt during a floating point divide.
2022-10-18 15:04:21 -05:00
Ross Thompson
9a7c7e8398
Added comments about planned changes.
2022-08-29 09:48:00 -05:00
David Harris
2170203847
Simplified FPU-LSU interface to skip IEU
2022-08-22 13:28:51 -07:00
Katherine Parry
41c16be012
srt divider merged into fpu
2022-07-07 16:01:33 -07:00
DTowersM
6944996329
added #1 delays to Stalls and Flushes in hazard unit
2022-06-08 16:28:09 +00:00
David Harris
1d8bc2dc1b
Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit
2022-06-02 09:37:59 -07:00
David Harris
faa15b1f8d
Cleaned up comments in controller
2022-06-02 15:48:33 +00:00
David Harris
c7ec9282fe
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
David Harris
4237bb7abd
Added comments to some files, added a+b = 0 detector to comparator.sv
2022-05-28 09:41:48 +00:00
David Harris
2ceed15bd5
Moved TLB Flush logic into privdec
2022-05-12 16:41:52 +00:00
David Harris
a516f89f22
WFI terminates when an interrupt is pending even if interrupts are globally disabled
2022-05-08 04:30:46 +00:00
David Harris
9b7aab122e
wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
2022-05-05 14:37:21 +00:00
David Harris
1a7599ce94
Changed WFI to stall pipeline in memory stage
2022-05-05 02:03:44 +00:00
David Harris
04b0579b89
Extended sim time to fully boot Linux. Added comments to hazard unit
2022-04-24 13:51:00 +00:00
David Harris
fd13272d4c
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
Ross Thompson
f870b8b3d3
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
1d8451c2cf
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
