Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
2,321 Commits 14 Branches 1 Tag 31 MiB
5904bc68c7
Commit Graph

129 Commits

Author SHA1 Message Date
Ross Thompson
5904bc68c7 Patched up the linux-wave.do file. 2021-12-30 17:53:43 -06:00
Ross Thompson
b6c9d01f8b Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu. 2021-12-30 14:56:17 -06:00
Ross Thompson
86514a6a23 icache separated from bus fetch fsm. Does not work yet. 2021-12-30 14:23:05 -06:00
Ross Thompson
9bcb105aa4 Changed names of Icache signals. 2021-12-30 11:01:11 -06:00
Ross Thompson
077bc35e10 Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu. 2021-12-29 22:24:37 -06:00
Ross Thompson
a16b97cfb4 Added default to busfsm. 2021-12-29 17:53:24 -06:00
Ross Thompson
90ccc94e5e Moved lsu interlock fpm to separate module. 2021-12-29 17:40:24 -06:00
Ross Thompson
81741925aa Moved LSU Bus interface control path into it's own module. 2021-12-29 17:35:45 -06:00
Ross Thompson
1730f644af Name cleanup in LSU. 2021-12-29 16:34:35 -06:00
Ross Thompson
050523487c Changed names of lsu address signals. 2021-12-29 15:03:34 -06:00
Ross Thompson
b1116600fe Added more generates around virtual memory and csrs in the lsu. 2021-12-29 14:48:09 -06:00
Ross Thompson
0c88ddeb5a Simplified the dcache to bus address generation. 2021-12-29 10:46:48 -06:00
Ross Thompson
6052a69ba7 Fixed interrupt delay bug by reverting CommittedM changes. 2021-12-28 22:27:12 -06:00
Ross Thompson
1894afd0d8 Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters. 
Fixed bug with the uncached memory operations.  The periph tests still do not pass.  They enter into what seems an intentional infinite loop.  Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
 2021-12-28 21:28:03 -06:00
Ross Thompson
39bd78c295 Changed the bus name between dcache and ebu. 2021-12-28 15:57:36 -06:00
Ross Thompson
13b4201198 Added generate around virtual memory hardware in LSU. 2021-12-28 15:00:02 -06:00
Ross Thompson
74d636cb53 First cut at moving the dcache bus interface into the LSU. 
Regression test does not run and there is a lot of cleanup to do.
 2021-12-27 18:12:59 -06:00
Ross Thompson
7fe70c3cc6 Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages. 
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.

There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment.  This can be cached in the TLB which only costs 1 flip flop
   for each TLB line.
 2021-12-23 12:40:22 -06:00
Ross Thompson
d3c3422d12 Rename of SelPTW to SelHPTW. 2021-12-19 22:24:07 -06:00
Ross Thompson
c9291655da Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass. 2021-12-19 16:12:31 -06:00
Ross Thompson
a445bedcd2 Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage. 
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
 2021-12-19 14:57:42 -06:00
Ross Thompson
225cd5a114 Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache. 2021-12-19 14:00:30 -06:00
Ross Thompson
1126135b80 minro change. comments about needed changes in dcache. 2021-12-19 13:53:02 -06:00
David Harris
0f319b45c1 Do File cleanups 2021-12-17 17:45:26 -08:00
David Harris
b3bded9e6c Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
Ross Thompson
e16c27225b Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00
Ross Thompson
615fd41e7b Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
cae350abb7 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
Ross Thompson
a15d6c1c96 Slight modification to wave file. 2021-09-08 10:40:46 -05:00
Ross Thompson
05455f8392 Changed name of memory in icache. 2021-09-06 20:54:52 -05:00
Ross Thompson
2968623f9a Partial multiway set associative icache. 2021-08-30 10:49:24 -05:00
Ross Thompson
96cbd8e785 Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. 
One downside is it increases the icache complexity.  However it also fixes an untested bug.  If a region
was uncacheable it would have been possible for the request to be made multiple times.  Now that is
not possible.  Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
 2021-08-27 11:03:36 -05:00
Ross Thompson
d6ff89b7e6 Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits. 2021-08-26 15:43:02 -05:00
Ross Thompson
e4bbd3bbc7 Converted the icache type from logic to state type. 2021-08-26 10:41:42 -05:00
Ross Thompson
0530047f53 Moved dcache fsm to separate module. 2021-08-25 21:37:10 -05:00
Ross Thompson
d23b860c96 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. 
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
 2021-08-25 21:09:42 -05:00
Ross Thompson
e9a1dc90f6 Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
55fda4de62 Switched ExceptionM to dcache to be just exceptions. 
Added test bench logic to hold forces until the W stage is unstalled.
 2021-08-13 15:53:50 -05:00
Ross Thompson
e166cc84ee Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files. 2021-07-30 14:24:50 -05:00
Ross Thompson
3e916da36e Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage.  Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM.  At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data.  When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
 2021-07-22 19:42:19 -05:00
Ross Thompson
551e3491af Moved the ReadDataW register into the datapath. 
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
 2021-07-22 14:52:03 -05:00
Ross Thompson
25a8920a69 Tested all numbers of ways for dcache 1, 2, 4, and 8. 2021-07-22 10:38:07 -05:00
Ross Thompson
313bc5255c Improved address bus names and usages in the walker, dcache, and tlbs. 
Merge branch 'walkerEnhance' into main
 2021-07-21 14:55:09 -05:00
Ross Thompson
e0990535e1 Fixed remaining bugs in 2 way set associative dcache. 2021-07-21 10:35:23 -05:00
Ross Thompson
14e949d6e3 Partially working 2 way set associative d cache. 2021-07-20 17:51:42 -05:00
Ross Thompson
b61dad4b83 Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW. 2021-07-19 12:32:16 -05:00
Ross Thompson
4d53b9002f Broken. 
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated.  This leads to incorrect index
selection in the dcache.
 2021-07-19 10:33:27 -05:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
b3bf04d474 Updated wave file. 2021-07-16 12:34:37 -05:00
Ross Thompson
46bce70e42 Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00