Xavi/cvw
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539d21645f
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980 Commits

Author SHA1 Message Date
Katherine Parry
539d21645f some fpu lint warnings fixed - still working on it 2021-10-11 18:32:03 -07:00
Shreya Sanghai
0acf9fd746 made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
Shreya Sanghai
84ff2b49c7 actually added redundant mul 2021-10-11 11:29:13 -07:00
Shreya Sanghai
a1c9ffdf2b added redundant multiplier 2021-10-11 11:20:12 -07:00
David Harris
ab6a796690 Starting to optimize multiplier 2021-10-11 11:06:07 -07:00
David Harris
f1190b6ceb intdiv cleanup 2021-10-11 08:14:21 -07:00
David Harris
4139f27d10 Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
75c17dc372 Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
David Harris
a6c6b2b974 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:26:15 -07:00
David Harris
caf3c2de9b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:25:11 -07:00
bbracker
90ccd60790 simplify flopenrc's that didn't actually need to be flopenrc's 2021-10-10 12:25:05 -07:00
David Harris
43d92f2507 Divider cleanup 2021-10-10 12:24:44 -07:00
David Harris
6704e37597 Simplifying divider FSM 2021-10-10 12:21:43 -07:00
David Harris
4deae8019a Simplifying divider FSM 2021-10-10 12:21:36 -07:00
David Harris
2759f1fcb1 Moved & ~StallM from FSM into DivStartE 2021-10-10 11:49:32 -07:00
David Harris
635fe181f8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
b713b6ca87 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
6988c8c37c divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
c2bb0324c6 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
David Harris
3aa9e088c8 Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
39bbeefa78 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
64ed267825 renamed DivSigned 2021-10-10 08:30:19 -07:00
Katherine Parry
77fe00947e FMA matches diagram and lint warnings fixed 2021-10-09 17:38:10 -07:00
kipmacsaigoren
96565f9435 rename adder in fpu for synthesis 2021-10-08 17:47:54 -05:00
kipmacsaigoren
7fde7aae6e Merging new changes into the old one's I've made in the OKstate servers 2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
f3058f94c6 removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions. 2021-10-08 15:33:18 -07:00
kipmacsaigoren
2d4623b49c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-08 12:01:44 -05:00
bbracker
1824b2af13 fix div restarting bug 2021-10-07 18:55:00 -04:00
kipmacsaigoren
8db7ce002d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-06 11:52:34 -05:00
James E. Stine
a91c0c8fc7 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
kipmacsaigoren
b72e94badf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-04 12:28:03 -05:00
David Harris
36bbf0c502 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
10ef563211 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
78eba19a1f Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
48e33c79a9 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
648cc8ef64 Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
2ae51d1852 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
81601e26a3 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
c690a863b5 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
David Harris
0c08a7c05c More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
5e6b2490cb Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
418e9cd6e6 Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
b3bded9e6c Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
5db800fac3 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
3a85c972b6 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
5d64f04752 Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
f913305993 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
afd6babc13 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
e33ef58e67 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
4926ae343a Divider code cleanup 2021-10-02 10:13:49 -04:00