David Harris
a6708ed887
cache cleanup
2022-02-03 15:36:11 +00:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
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2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
325724f556
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
c97572d209
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
David Harris
2a64b1bc95
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
0fddceffa6
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
...
assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
Ross Thompson
008ac20a43
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
Ross Thompson
e1db967417
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
Ross Thompson
d30ad136f3
cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
2022-01-05 22:56:18 -06:00
Ross Thompson
365b2715ed
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
77efcad15b
Changed names of address in caches.
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Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
8d33bf0b4a
Slower but correct implementation of flush.
2022-01-05 16:57:22 -06:00
Ross Thompson
bd901cd125
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 14:15:27 -06:00
Ross Thompson
49eea2add5
Fixed bug with flush dirty not cleared in the correct cache line.
2022-01-05 14:14:01 -06:00
David Harris
32590d484c
Removed more generate statements
2022-01-05 16:25:08 +00:00
David Harris
f04856ee94
Removed more generate statements
2022-01-05 16:01:03 +00:00
Ross Thompson
f89c1d91dc
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
9eda7c12bd
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
Ross Thompson
b06c3b8acd
parameterized the caches with the goal of using common rtl for both i and d caches.
2022-01-04 22:40:51 -06:00
Ross Thompson
06168e67e4
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
Ross Thompson
d94a1c6404
Fixed bug where last line of dcache was not written back to memory on dcache flush.
2022-01-04 21:55:48 -06:00
Ross Thompson
3c3c6d0fe8
Fixed dcache flush.
2022-01-04 18:40:58 -06:00
David Harris
1f07470477
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
