David Harris
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fe3147806d
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removed simpleram and modified dtim to use bram1p1rw
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2022-08-25 03:39:57 -07:00 |
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David Harris
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b3a13a01f8
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Stripped write capaibilty out of rom_ahb
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2022-08-24 17:23:08 -07:00 |
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Ross Thompson
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b650d7e05a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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c636387613
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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Ross Thompson
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07b2858890
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added SD card and external ram to common testbench.
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2022-08-24 13:27:18 -05:00 |
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Ross Thompson
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c6927d2ace
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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David Harris
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9e3d13ca52
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Q depends on D
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2022-08-23 08:29:59 -07:00 |
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David Harris
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7c91ed38a3
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LSU minor edits
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2022-08-23 07:35:47 -07:00 |
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David Harris
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b795cf4731
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Updated testbench assertions.
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2022-08-23 07:23:24 -07:00 |
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Ross Thompson
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21526957cf
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
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Ross Thompson
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dad6770fc3
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Updated fpga testbench.
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2022-08-21 14:07:26 -05:00 |
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Katherine Parry
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0f077012c3
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sqrt tests in regression uncommented and pass
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2022-08-07 23:38:10 +00:00 |
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Katherine Parry
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8eeca3319c
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radix-2 1 copy passes testfloat
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2022-08-06 22:54:05 +00:00 |
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David Harris
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8b8f045491
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Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
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David Harris
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6ee8036ae7
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plic-s debug
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2022-08-03 12:33:09 +00:00 |
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David Harris
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e3b970d3ff
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Partitioned fma into separate files
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2022-08-01 18:07:38 +00:00 |
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David Harris
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da275e3c26
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Increased timeout threshold to avoid timeout building riscof tests on slow machine
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2022-07-27 04:05:21 +00:00 |
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David Harris
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ae4ea00ff0
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fixed testbench merge comflict
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2022-07-26 06:21:46 -07:00 |
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David Harris
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449c80b5f7
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More work toward riscof tests
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2022-07-26 06:19:13 -07:00 |
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David Harris
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094aacdf6f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-25 23:29:08 +00:00 |
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David Harris
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ccf8ccfa24
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Added rv32f tests to RV64gc
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2022-07-25 23:29:05 +00:00 |
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David Harris
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539174f6f6
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Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
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2022-07-25 16:23:10 -07:00 |
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Ross Thompson
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70032bf8f4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-23 08:41:59 -05:00 |
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Katherine Parry
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ee7932c804
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divider sizes reworked to match book
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2022-07-22 22:02:04 +00:00 |
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Daniel Torres
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d95b266d49
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changes to test.vh for compatability
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2022-07-22 15:00:48 -07:00 |
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Daniel Torres
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2bbfd67082
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added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
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2022-07-22 14:58:55 -07:00 |
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slmnemo
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44c30ec082
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fixed error in tests.vh
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2022-07-22 14:55:55 -07:00 |
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slmnemo
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170601af0b
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Added UART test to peripheral test
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2022-07-22 14:55:34 -07:00 |
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Daniel Torres
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fbe3a1af12
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 13:52:19 -07:00 |
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Daniel Torres
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261b9aa5a1
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commented out embench test that should be commented out
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2022-07-22 13:52:13 -07:00 |
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slmnemo
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0d98ff74b4
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Added PLIC test to regression
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2022-07-22 12:35:37 -07:00 |
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Daniel Torres
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5d7171f6f8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 11:16:09 -07:00 |
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Daniel Torres
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526f70e772
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commiting current changes to riscof wally tests
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2022-07-22 11:14:04 -07:00 |
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slmnemo
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49565f944c
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Added PLIC and UART tests and new functions to the test library
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2022-07-22 07:10:39 -07:00 |
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Daniel Torres
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bd918d37ba
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added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
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2022-07-21 20:58:58 -07:00 |
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Daniel Torres
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a17361870f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 12:50:04 -07:00 |
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Daniel Torres
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6e9b4f4075
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removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
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2022-07-21 12:47:51 -07:00 |
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Katherine Parry
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270216dd02
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radix-4 division integrated into srt - not tested
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2022-07-21 19:38:06 +00:00 |
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Katherine Parry
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67c99d3d1a
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added input enables and improved forwarding
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2022-07-21 01:20:06 +00:00 |
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Daniel Torres
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d33d0d22bd
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commented out embench 2.0 tests
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2022-07-19 13:36:18 -07:00 |
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Katherine Parry
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4c2afbbc4f
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moved Se into execute stage
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2022-07-19 01:10:10 +00:00 |
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Katherine Parry
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e599f82b29
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moved Ss to execute stage
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2022-07-18 20:48:56 +00:00 |
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Katherine Parry
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921debf930
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removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Katherine Parry
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5bb1478859
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renamed signals in ocde to match book
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2022-07-18 17:31:17 +00:00 |
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Ross Thompson
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a88543275f
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Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
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2022-07-17 21:05:31 -05:00 |
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Ross Thompson
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3670c47141
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Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
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2022-07-17 16:20:04 -05:00 |
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Katherine Parry
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e251022269
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merged floating-point radix-2 divider with radix-4
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2022-07-15 20:16:59 +00:00 |
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Katherine Parry
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b069cfbec2
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fixed error in divsqrt
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2022-07-14 18:16:00 +00:00 |
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Katherine Parry
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77ea4e47cb
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removed minus 1 case in rounding
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2022-07-13 15:01:38 -07:00 |
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Katherine Parry
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e05b2a07d2
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removed warnings and took a mux out of the critical path
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2022-07-12 18:32:17 -07:00 |
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