Katherine Parry
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254ebf478e
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added fld in rv32 - needs testing
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2022-06-20 22:53:13 +00:00 |
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slmnemo
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054cf5f7b0
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Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
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2022-06-08 15:03:15 -07:00 |
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slmnemo
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284e0395a0
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Merge branch 'main' into cacheburstmode
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2022-06-08 02:21:33 +00:00 |
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slmnemo
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2d76953d42
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Added lock signal to ensure AHB speaks with the right bus
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2022-06-08 02:19:21 +00:00 |
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slmnemo
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73e0c1c07f
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Reworked bus to handle burst interfacing
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2022-06-07 11:22:53 +00:00 |
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David Harris
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c7ec9282fe
|
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
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2022-06-02 14:18:55 +00:00 |
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slmnemo
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847c7930c4
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added LSUBurstDone signal to signal when a burst has finished
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2022-05-26 16:29:13 -07:00 |
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slmnemo
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08430a1e85
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added burst size signals to the IFU, EBU, LSU, and busdp
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2022-05-25 18:02:50 -07:00 |
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David Harris
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5670f77de2
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More unused signal cleanup
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2022-05-12 15:21:09 +00:00 |
|
David Harris
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e2e63ca9a8
|
Clean up unused signals
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2022-05-12 14:49:58 +00:00 |
|
David Harris
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4f1b0fdc64
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
|
David Harris
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22842816a8
|
LSU name cleanup
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2022-04-18 03:18:38 +00:00 |
|
David Harris
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c07b9d1722
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Renamed FinalAMOWriteDataM to AMOWriteDataM
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2022-04-18 01:30:03 +00:00 |
|
Ross Thompson
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bfc68bef69
|
Fixed possible bugs in LRSC.
|
2022-04-16 14:45:31 -05:00 |
|
Ross Thompson
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396f697d2f
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Hacky fix to prevent ITLBMissF and TrapM bug.
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2022-04-12 17:56:23 -05:00 |
|
Ross Thompson
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fe896bff8e
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Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
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2022-03-24 23:47:28 -05:00 |
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Ross Thompson
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71aad2d213
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Moved WriteDataM register into LSU.
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2022-03-23 14:17:59 -05:00 |
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Ross Thompson
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8f74fd2a50
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-23 14:10:38 -05:00 |
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Ross Thompson
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b2487f4b72
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-22 21:28:50 -05:00 |
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Ross Thompson
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ca8fb45367
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Added comment about needed fix to misaligned fault.
|
2022-03-22 16:52:07 -05:00 |
|
Ross Thompson
|
ee4b38dce3
|
dtim writes are supressed on non cacheable operation.
|
2022-03-12 00:46:11 -06:00 |
|
Ross Thompson
|
86cc758354
|
cleanup of ram.sv
|
2022-03-11 18:09:22 -06:00 |
|
Ross Thompson
|
67ff8f27f4
|
Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
|
2022-03-11 15:18:56 -06:00 |
|
Ross Thompson
|
9dce2a0679
|
Towards allowing dtim + bus.
|
2022-03-11 14:58:21 -06:00 |
|
Ross Thompson
|
b7a680ec2a
|
Moved subcachelineread inside the cache. There is some ugliness to still resolve.
|
2022-03-11 12:44:04 -06:00 |
|
Ross Thompson
|
a18f06c20b
|
Moved subcacheline read inside the cache.
|
2022-03-11 11:03:36 -06:00 |
|
Ross Thompson
|
52cc852600
|
removed unused parameter.
|
2022-03-11 10:43:54 -06:00 |
|
Ross Thompson
|
7f0c5cc847
|
atomic cleanup.
|
2022-03-10 18:56:37 -06:00 |
|
Ross Thompson
|
257015a2df
|
Name changes.
|
2022-03-10 18:50:03 -06:00 |
|
Ross Thompson
|
6d914def08
|
Name cleanup.
|
2022-03-10 18:44:50 -06:00 |
|
Ross Thompson
|
63b1ea88c9
|
Signal name cleanup.
|
2022-03-10 18:26:58 -06:00 |
|
Ross Thompson
|
396c97fc36
|
Byte write enables are passing all configs now.
|
2022-03-10 17:26:32 -06:00 |
|
Ross Thompson
|
d8e71e8e35
|
Progress on the path to getting all configs working with byte write enables.
|
2022-03-10 17:02:52 -06:00 |
|
Ross Thompson
|
67ef46ea92
|
Partially working byte write enables. Works for cache, but not dtim or bus only.
|
2022-03-10 16:11:39 -06:00 |
|
Ross Thompson
|
7a129c75cd
|
Added byte write enables to cache SRAMs.
|
2022-03-10 15:48:31 -06:00 |
|
Ross Thompson
|
0310fe858f
|
Comments.
|
2022-03-08 18:05:25 -06:00 |
|
Ross Thompson
|
3ec32d7ce8
|
Removed unused signal.
|
2022-03-08 16:58:26 -06:00 |
|
Ross Thompson
|
7b96b3f73c
|
Moved cacheable signal into cache.
|
2022-03-08 16:34:02 -06:00 |
|
David Harris
|
2cea3349ad
|
LSU/Cache code review notes
|
2022-03-04 00:07:31 +00:00 |
|
Ross Thompson
|
59f04f2518
|
Minor busdp cleanup.
|
2022-02-22 17:28:26 -06:00 |
|
Ross Thompson
|
456a54166a
|
Minor cleanup of lsu.
|
2022-02-21 12:46:06 -06:00 |
|
Ross Thompson
|
5d9ad011d2
|
Moved mux into lsuvirtmem.
|
2022-02-21 09:31:29 -06:00 |
|
Ross Thompson
|
a60332b455
|
Minor changes to LSU.
|
2022-02-19 14:38:17 -06:00 |
|
Ross Thompson
|
d152733a17
|
Rough implementation passing regression test with hptw atomic writes to memory.
|
2022-02-17 14:46:11 -06:00 |
|
Ross Thompson
|
565ca4e4a3
|
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
|
2022-02-16 23:37:36 -06:00 |
|
Ross Thompson
|
beac362364
|
Moved a few muxes around after sww changes.
|
2022-02-16 15:43:03 -06:00 |
|
Ross Thompson
|
6a2bcfcd01
|
cleanup of signal names.
|
2022-02-16 15:29:08 -06:00 |
|
Ross Thompson
|
bd7343b791
|
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
|
2022-02-16 15:22:19 -06:00 |
|
Ross Thompson
|
7ffbc6b2ab
|
Changed names of signals in cache.
|
2022-02-13 15:06:18 -06:00 |
|
Ross Thompson
|
1c83914662
|
Fixed bug.
It was possible for DTLBMissM to prevent a dcache flush.
|
2022-02-11 14:00:01 -06:00 |
|