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472fb5e888
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Author SHA1 Message Date
Ross Thompson
472fb5e888 Renamed states in busfsm to match AHB phases and book names. 2022-09-02 17:12:36 -05:00
Ross Thompson
15a2fbdd33 Possible fix for AHB trailing ~HREADY bug. 2022-09-02 16:58:35 -05:00
Ross Thompson
851ad4417d Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 16:31:07 -05:00
Ross Thompson
c7055a3ee2 update to fpga wave. 2022-09-02 15:54:54 -05:00
Ross Thompson
2aa5886769 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
722e1a029e Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 13:54:48 -05:00
Ross Thompson
559e093ab5 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
Ross Thompson
83c427c5b5 clean up subword write. 2022-09-01 17:55:19 -05:00
Ross Thompson
5b4e744972 marked possible improvement to ahb bus fsms. 2022-08-31 23:57:08 -05:00
Ross Thompson
5c8631fd16 Reduced busfsm to 3 states! 2022-08-31 16:11:59 -05:00
Ross Thompson
1cd7d8dbfe Simplified. 2022-08-31 15:40:56 -05:00
Ross Thompson
2b528dc8be more renaming. 2022-08-31 14:52:06 -05:00
Ross Thompson
ab4c75cbf5 More renaming. 2022-08-31 14:49:08 -05:00
Ross Thompson
6e85f850a4 Moved files. 
Encapsulated ahbinterface.
 2022-08-31 14:45:01 -05:00
Ross Thompson
fcd1465de1 Renamed AHBCachebusdp to abhcacheinterface. 2022-08-31 14:12:19 -05:00
Ross Thompson
d6d1c5d66d Moved files around. 2022-08-31 14:08:06 -05:00
Ross Thompson
08d0c1cc83 Major cleanup of multimanager. 2022-08-31 12:40:25 -05:00
Ross Thompson
352f7443c2 Cleanup multimanager. 2022-08-31 12:04:44 -05:00
Ross Thompson
1e752c1268 cleanup of multimanager. 2022-08-31 11:38:06 -05:00
Ross Thompson
1663f571ed More Cleanup. 2022-08-31 11:21:02 -05:00
Ross Thompson
68e54977fe More cleanup. 2022-08-31 11:12:38 -05:00
Ross Thompson
0b41ed63f1 More simplifications. 2022-08-31 10:45:16 -05:00
Ross Thompson
ddd9c507fe Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier. 2022-08-31 10:36:30 -05:00
Ross Thompson
6122c03e39 Removed unused old versions of the bus controllers. 2022-08-31 09:51:54 -05:00
Ross Thompson
1c248e5164 Removed old signals. 2022-08-31 09:50:39 -05:00
Ross Thompson
5b8f888e21 Maybe fixed it? 2022-08-30 18:08:34 -05:00
Ross Thompson
ccb3e9e24e Updates to wave file. 2022-08-30 17:34:36 -05:00
Ross Thompson
96793d15c0 more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
2d6a6c6e44 Temporary commit. 2022-08-30 15:40:42 -05:00
Ross Thompson
63a824cca1 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
a532eb61ba Progress. 2022-08-30 14:17:00 -05:00
Ross Thompson
c8a5d61cbb new cache bus fsm not working but lints. 
Forgot a few files in the last commit.
 2022-08-30 10:58:07 -05:00
Ross Thompson
5eb1fff27d Have a rough working multi manager! 2022-08-29 17:11:27 -05:00
Ross Thompson
4f40bd07c3 Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu. 2022-08-29 17:04:53 -05:00
Ross Thompson
4d7b905806 Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager. 2022-08-29 13:01:24 -05:00
Ross Thompson
40cf4a9ea9 Typo. 2022-08-29 11:40:35 -05:00
Ross Thompson
1c9aed2e7e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 11:38:37 -05:00
Ross Thompson
9a7c7e8398 Added comments about planned changes. 2022-08-29 09:48:00 -05:00
David Harris
6961e499dc Renamed special case 2022-08-29 04:29:58 -07:00
David Harris
81ec1ac858 Separated out radix 2 and radix 4 stages into different modules 2022-08-29 04:26:14 -07:00
David Harris
b4cb9a678a renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
Ross Thompson
35d0b759d1 Removed ignore request from busfsm. 2022-08-28 21:12:27 -05:00
Ross Thompson
dd00474956 Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
Ross Thompson
e3e1f29428 Reordered the adrdecs. 2022-08-28 13:38:57 -05:00
Ross Thompson
99e0e5c817 Possible fix. 2022-08-28 13:10:47 -05:00
Ross Thompson
5e77b1bd2b Partial fix to bus + dtim. 2022-08-27 23:44:17 -05:00
David Harris
35d0a951d2 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
David Harris
3959902c5b Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus 2022-08-27 05:31:56 -07:00
David Harris
e526fea68a fixed wally-config 2022-08-26 22:13:10 -07:00
David Harris
bd6f2444cd Fixed address decoder hanging buildroot 2022-08-26 22:01:25 -07:00