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Author SHA1 Message Date
Teo Ene
9c4a117ffb When Alex taught me how to use git, he stressed the importance of good commit messages that properly describe what changes were made 2021-02-12 16:52:23 -06:00
Teo Ene
db17d59698 Fixed rm bug for Ryan 2021-02-12 16:36:04 -06:00
Teo Ene
cc077da2bb Removed riscv-o3 module 2021-02-12 16:08:34 -06:00
Teo Ene
f25b372c32 Quick commit for Ryan / branch / debugging. 2021-02-12 16:06:02 -06:00
Noah Boorstin
423d3a53e5 add reference output for some tests 2021-02-12 18:33:24 +00:00
bbracker
9231646fb3 bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
Tejus Rao
5158ca4220 added test cases for ADDW, SUBW, SLLW, SRLW, SRAW 2021-02-11 13:38:38 -05:00
Teo Ene
dfb7333821 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-02-10 20:49:12 -06:00
Teo Ene
8a6de4fb86 Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts 2021-02-10 20:48:39 -06:00
Teodor-Dumitru Ene
86fcaf0bb1 Added hex code for the pre-compiled, provided, CoreMark binary 2021-02-10 21:22:38 -05:00
Teo Ene
7ca03b2b38 Added freshly compiled CoreMark binaries (elf) and hex code (memfile) for the following extensions: 
- RV64I
 2021-02-10 20:12:07 -06:00
ethan-falicov
9edc4b6bfe Fixed merge conflict stuff 2021-02-10 10:03:30 -05:00
ethan-falicov
7e8a58de1a More merge conflicts yay 2021-02-10 09:54:30 -05:00
ethan-falicov
f778f464b7 Merge conflict fixing 2021-02-10 09:45:47 -05:00
ethan-falicov
06541260e0 Adding I Type test cases from Lab 1 2021-02-10 09:39:43 -05:00
David Harris
183a2dcfb5 Debugging bus interface. 2021-02-10 01:43:54 -05:00
James E. Stine
561ffcf56d Add ppt and mp4 of wavedrom usage 2021-02-09 13:15:29 -06:00
David Harris
2357f5513b Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
63c7c18771 Fixed lw by delaying read value by one cycle 2021-02-07 23:28:21 -05:00
David Harris
3551cc859b Data memory bus integration 2021-02-07 23:21:55 -05:00
Jarred Allen
403a0d033c Fix compile error in imperas testbench 2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
81a1eb9a74 merge conflict? 2021-02-07 02:34:49 -05:00
Jarred Allen
48ade25577 Actually run the WALLY-LOAD tests 2021-02-06 14:56:40 -05:00
Jarred Allen
edd758453e Add test vector set for load instructions 2021-02-06 13:05:59 -05:00
James E. Stine
5c017bac1f Updates to wavedrom 2021-02-05 10:56:29 -06:00
bbracker
691d651fde JAL testing 2021-02-05 08:08:42 -05:00
James E. Stine
eb468cc40f sorry ; last update 2021-02-04 15:20:15 -06:00
James E. Stine
0eae86b6e3 Update as overwrite a file :( 2021-02-04 15:11:06 -06:00
James E. Stine
c259cd2e7e Updates to wavedrom for typos 2021-02-04 14:49:17 -06:00
James E. Stine
a3bd34eb4b Add some example wavedrom files - more on the way including ppt 2021-02-04 14:41:42 -06:00
Thomas Fleming
8588a1ed6b Complete STORE tests 2021-02-04 15:38:22 -05:00
Brett Mathis
79cb7ed571 Parallel FSR's and F CTRL logic 2021-02-04 02:25:55 -06:00
Jarred Allen
ea791cb057 Change busybear test to use work-busybear library 2021-02-03 11:12:47 -05:00
Jarred Allen
743695400d Start on a test set for loads 2021-02-03 00:37:43 -05:00
David Harris
91f6858de7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-02 19:44:43 -05:00
David Harris
a44c2abb12 Minor tweaks 2021-02-02 19:44:37 -05:00
Jarred Allen
10f023b44d Refactor regression test 2021-02-02 17:22:29 -05:00
Noah Boorstin
b370be4a8a Add busybear testbench to nightly regression checking 
If you don't like how I did this please feel free to undo it
 2021-02-02 22:05:35 +00:00
Noah Boorstin
00d9e13d68 same thing but do that right this time 2021-02-02 21:47:15 +00:00
Noah Boorstin
56ff32f857 change undefined syntax in extend.sv 
don't need verilator execption anymore
 2021-02-02 21:39:20 +00:00
David Harris
d56d7a75a6 Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
David Harris
aee44bb343 Changed DTIM latency to 2 cycles 2021-02-02 14:22:12 -05:00
David Harris
4fbb5f0f1b Cleaned up hazard interface 2021-02-02 13:53:13 -05:00
David Harris
e661b32821 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-02 13:42:35 -05:00
David Harris
c23afbda3a Moved LoadStall generation to IEU 2021-02-02 13:42:23 -05:00
David Harris
aad1d3d7dd Moved writeback pipeline registers from datapth into DMEM and CSR 2021-02-02 13:02:31 -05:00
Jarred Allen
5090537f3c Fix intermittent errors caused by weird library stuff 2021-02-02 11:20:09 -05:00
Jarred Allen
8dcb4b2d57 Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
Noah Boorstin
8d53e36bbc Busybear: start checking CSRs 
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)

and 3 of the CSRs referenced are skipped because of weird locations for them

oh and this doesn't check their initial state, just their changing. This could be a problem
 2021-02-02 06:06:03 +00:00
David Harris
9d7e242596 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00